UTRON
UT62L6416
64K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
℃
CAPACITANCE (TA=25 , f=1.0MHz)
PARAMETER
Input Capacitance
SYMBOL
MIN.
-
-
MAX
6
8
UNIT
pF
pF
CIN
CI/O
Input/Output Capacitance
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
5ns
1.5V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
CL = 30pF, IOH/IOL = -1mA / 2.1mA
℃
℃
℃
℃
AC ELECTRICAL CHARACTERISTICS
(VCC =2.7V~3.6V, TA =0 to 70 / -20 to 85 (E))
(1) READ CYCLE
PARAMETER
SYMBOL
UT62L6416-55
UT62L6416-70
UNIT
MIN.
55
-
-
MAX.
MIN.
70
-
-
-
10
5
-
-
10
-
MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
30
-
70
70
35
-
-
10
5
-
-
10
-
-
-
20
20
-
25
25
-
tBA
55
70
,
Access Time
LB UB
tBHZ
tBLZ
-
25
-
-
30
-
ns
ns
,
to High-Z Output
to Low-Z Output
LB UB
10
10
,
LB UB
(2) WRITE CYCLE
PARAMETER
SYMBOL
UT62L6416-55
UT62L6416-70
UNIT
MIN.
55
50
50
0
45
0
25
0
MAX.
MIN.
MAX.
Write Cycle Time
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
-
-
-
-
-
-
-
-
-
70
60
60
0
55
0
30
0
5
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
tOW*
tWHZ*
tBW
5
-
45
30
-
-
60
30
-
,
Valid to End of Write
LB UB
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
P80073
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
5