Datasheet > UT62L1024PC-55LL

UT62L1024PC-55LL

更新时间： 2024-11-19 22:16:31

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
14页	235K
描述
128K X 8 BIT LOW POWER CMOS SRAM

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中文翻译

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数据手册

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UT62L1024PC-55LL 数据手册



UTRON

UT62L1024

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

FEATURES

GENERAL DESCRIPTION

Access time : 35/55/70ns (max.)

The UT62L1024 is a 1,048,576-bit low power

CMOS static random access memory organized

as 131,072 words by 8 bits. It is fabricated using

high performance, high reliability CMOS

technology.

Low power consumption :

Operating : 40/35/30 mA (typical)

Standby : 2.5µA (typical) L-version

0.5µA (typical) LL-version

Power supply range : 2.7V to 3.6V

Easy memory expansion is provided by using

All inputs and outputs TTL compatible

Fully static operation

two chip enable input.(

,CE2) It is

CE1

Three state outputs

particularly well suited for battery back-up

nonvolatile memory application.

Data retention voltage : 2V (min.)

Package : 32-pin 600 mil PDIP

32-pin 450 mil SOP

The UT62L1024 operates from a single 2.7V~

3.6V power supply and all inputs and outputs

are fully TTL compatible.

32-pin 8x20 mm TSOP-1

32-pin 8x13.4 mm STSOP

FUNCTIONAL BLOCK DIAGRAM

2048 512

A0-A16

DECODER

MEMORY

ARRAY

Vcc

Vss

I/O DATA

CIRCUIT

I/O1-I/O8

COLUMN I/O

CE1

CE2

CONTROL

CIRCUIT

UTRON TECHNOLOGY INC.

P80033

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

12 3 4 5 6 7...14

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