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UPD800261F1-523-HN2

更新时间： 2024-09-16 19:51:39
品牌 Logo 应用领域
瑞萨 - RENESAS 局域网外围集成电路
页数 文件大小 规格书
49页 414K
描述
IC,LAN NODE CONTROLLER,MOS,BGA,304PIN

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中文翻译

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UPD800261F1-523-HN2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
JESD-30 代码：S-PBGA-B304端子数量：304
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：FBGA
封装等效代码：BGA304,22X22,32封装形状：SQUARE
封装形式：GRID ARRAY, FINE PITCH电源：1.5 V
认证状态：Not Qualified子类别：Serial IO/Communication Controllers
最大压摆率：535 mA标称供电电压：1.5 V
表面贴装：YES技术：MOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches：1

UPD800261F1-523-HN2 数据手册

 浏览型号UPD800261F1-523-HN2的Datasheet PDF文件第2页浏览型号UPD800261F1-523-HN2的Datasheet PDF文件第3页浏览型号UPD800261F1-523-HN2的Datasheet PDF文件第4页浏览型号UPD800261F1-523-HN2的Datasheet PDF文件第5页浏览型号UPD800261F1-523-HN2的Datasheet PDF文件第6页浏览型号UPD800261F1-523-HN2的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD800261  
ERTEC 200  
Enhanced Real-Time Ethernet Controller  
with 32-bit RISC CPU Core  
DESCRIPTION  
ERTEC 200 is a powerful communication block for development of industrial Ethernet devices. ERTEC  
200 contains a 32-bit RISC processor, an external memory interface with SDRAM and SRAM control-  
ler, an LBU interface, a 2-channel real-time Ethernet interface with integrated PHYs, synchronous and  
asynchronous serial ports, and general purpose I/Os. Its robust construction, specific automation func-  
tions, and openness to the IT world are distinguishing features. The ERTEC 200 is housed in a 304-pin  
plastic FBGA package (19 mm × 19 mm).  
Detailed functions are described in the following user’s manual. Be sure to read this manual  
when you design your systems.  
Preliminary User’s Manual ERTEC 200  
: A17988EE1V0UM00  
FEATURES  
•
ARM946E-S core with max. 150 MHz  
•
•
Local bus unit (LBU) with 16-bit data bus to  
connect external host with access to internal  
ERTEC 200 resources  
IRT switch block with 2 Ethernet ports  
(10/100 Mbps) supporting RT and IRT traffic  
- integrated Ethernet PHYs  
- autonegotiation, broadcast filter  
- 64 kBytes internal communication SRAM  
one UART (16550 like) and one SPI interface  
two 32-bit timers with prescaler, one 16-bit  
timer, one 32-bit F-timer and two watchdog  
timers  
Max. 45 GPIOs, partly usable as interrupts  
- Max. 32 GPIOs, if LBU interface is used  
Various configuration options selectable during  
reset  
- 8 kBytes of instruction cache  
- 4 kBytes of data cache  
- 4 kBytes of D-TCM  
- Memory protection unit  
- On-chip debug and trace functionality via  
JTAG interface  
- ETM9 embedded trace macrocell  
- Interrupt controller for 16 IRQs and 8 FIQs  
Internal Multilayer AHB bus running at 50 MHz  
External memory interface (EMIF) supports up  
to 128 MBytes of SDRAM and up to 64 MBytes  
for static memories and I/O with 4 chip selects  
Single-channel DMA controller for high-speed  
memory-to-memory transfers and for serial  
interface support  
•
•
•
•
•
•
•
•
•
•
1.5 V (logic) and 3.3 V (I/O) power supply  
Temperature range: TA = -40 to 85°C  
Compact 304-pin plastic FBGA package  
•
•
Integrated PLL to generate internal clocks for  
ARM946E-S, AHB, APB and IRT switch  
Predefined Boot ROM content supporting  
different download sources  
ORDERING INFORMATION  
Device  
Part Number  
Package  
µPD800261F1-523-HN2  
µPD800261F1-523-HN2-A  
ERTEC 200  
P-FBGA304, 19 × 19 mm  
Remark: Products with -A at the end of the part number are lead-free products.  
The information in this document is subject to change without notice. Before using this document, please confirm that  
this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative  
for availability and additional information.  
© NEC Electronics Corporation 2007  
Document No. A17989EE1V1DS00  
Data Published: May 2007  
1234567...49

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