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UPD705100GJ-100-8EU PDF预览

UPD705100GJ-100-8EU

更新时间: 2024-09-12 22:07:27
品牌 Logo 应用领域
日电电子 - NEC 微控制器和处理器外围集成电路微处理器时钟
页数 文件大小 规格书
66页 507K
描述
V830TM 32-BIT MICROCONTROLLER

UPD705100GJ-100-8EU 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:20 X 20 MM, FINE PITCH, PLASTIC, QFP-144Reach Compliance Code:compliant
风险等级:5.88Is Samacsys:N
地址总线宽度:32位大小:32
边界扫描:NO最大时钟频率:100 MHz
外部数据总线宽度:32格式:FIXED POINT
集成缓存:NOJESD-30 代码:S-PQFP-G144
JESD-609代码:e0长度:20 mm
低功率模式:YES端子数量:144
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:3 mm速度:100 MHz
标称供电电压:3.3 V表面贴装:YES
技术:CMOS端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:20 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

UPD705100GJ-100-8EU 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD705100  
V830TM  
32-BIT MICROCONTROLLER  
The µPD705100 (also called V830) is a microcontroller for incorporation use, which belongs to the V830 familyTM  
of the NEC original V800 seriesTM microcontrollers. The V830 can achieve high cost-performance for multimedia  
equipment, by integrating quick real-time responses, high-speed arithmetic/logical instructions, and functions suitable  
for individual applications.  
The following user’s manual describes details of the functions of the V830. Be sure to read it before  
designing an application system.  
V830 User’s Manual, Hardware  
: U10064E  
V830 User’s Manual, Architecture : U12496E  
FEATURES  
High-performance 32-bit architecture for  
incorporation use  
16-bit bus fixing function  
16-bit bus system construction  
• Built-in cache memory  
Instructions suitable for variable application  
Instruction cache : 4K bytes  
Sum-of-products operation  
Saturable operation  
Data cache  
• Built-in RAM  
Instruction RAM  
Data RAM  
: 4K bytes  
Branch prediction  
: 4K bytes  
: 4K bytes  
Concatenation shift  
Block transfer instructions  
• One-clock-pitch pipeline structure  
• 16-/32-bit instructions  
Power-saving mode  
Maximum operating frequency  
• Separate buses for addresses and data  
• 4G-byte linear addresses  
100 MHz (internal)  
50/33 MHz (external)  
• Thirty-two 32-bit general-purpose registers  
• Hardware-interlocked register/flag hazard  
• 16-level interrupt responses  
CMOS operation, 3.3-V operation  
ORDERING INFORMATION  
Part number  
Package  
144-pin plastic LQFP (fine pitch) (20 × 20 mm)  
µPD705100GJ-100-8EU  
The information in this document is subject to change without notice.  
Document No. U11483EJ3V0DS00 (3rd edition)  
Date Published January 1998 J CP(K)  
Printed in Japan  
The mark  
shows major revised points.  
1995, 1996  
©

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