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UPD703204F1-XXX-EA6 PDF预览

UPD703204F1-XXX-EA6

更新时间: 2024-09-14 22:41:07
品牌 Logo 应用领域
日电电子 - NEC 微控制器和处理器外围集成电路时钟
页数 文件大小 规格书
98页 774K
描述
32-BIT SINGLE-CHIP MICROCONTROLLERS

UPD703204F1-XXX-EA6 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:12 X 12 MM, LEAD FREE, PLASTIC, BGA-121Reach Compliance Code:compliant
风险等级:5.86Is Samacsys:N
具有ADC:YES地址总线宽度:24
位大小:32最大时钟频率:20 MHz
DAC 通道:YESDMA 通道:YES
外部数据总线宽度:16JESD-30 代码:S-PBGA-B121
JESD-609代码:e0长度:12 mm
I/O 线路数量:102端子数量:121
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not QualifiedROM可编程性:MROM
座面最大高度:1.58 mm速度:20 MHz
最大供电电压:2.7 V最小供电电压:2.2 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:12 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

UPD703204F1-XXX-EA6 数据手册

 浏览型号UPD703204F1-XXX-EA6的Datasheet PDF文件第2页浏览型号UPD703204F1-XXX-EA6的Datasheet PDF文件第3页浏览型号UPD703204F1-XXX-EA6的Datasheet PDF文件第4页浏览型号UPD703204F1-XXX-EA6的Datasheet PDF文件第5页浏览型号UPD703204F1-XXX-EA6的Datasheet PDF文件第6页浏览型号UPD703204F1-XXX-EA6的Datasheet PDF文件第7页 
PRELIMINARY PRODUCT INFORMATION  
MOS INTEGRATED CIRCUIT  
µ
PD703201, 703201Y, 703204, 703204Y,  
70F3201, 70F3201Y, 70F3204, 70F3204Y  
V850ES/SA2TM, V850ES/SA3TM  
32-BIT SINGLE-CHIP MICROCONTROLLERS  
DESCRIPTION  
The µPD703201, 703201Y, 70F3201, and 70F3201Y (V850ES/SA2), µPD703204, 703204Y, 70F3204, and  
70F3204Y (V850ES/SA3) are products in the V850 FamilyTM of 32-bit single-chip microcontrollers, and include  
peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, and a  
DMA controller.  
In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/SA2  
and V850ES/SA3 include instructions suited to digital servo control applications such as multiplication instructions  
executed via a hardware multiplier, saturation instructions, and bit manipulation instructions. As a real-time control  
system, this device provides a high-level cost performance ideal for ultra-low-power DVC and portable audio  
applications.  
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before  
designing.  
V850ES/SA2, V850ES/SA3 User’s Manual Hardware:  
V850ES User’s Manual Architecture:  
To be prepared  
To be prepared  
FEATURES  
{ Number of instructions: 83  
{ Interrupts and exceptions  
{ Minimum instruction execution time:  
59 ns (@ 17 MHz operation with main system clock (fXX))  
74 ns (@ 13.5 MHz operation with main system clock (fXX))  
{ General-purpose registers: 32 bits × 32 registers  
{ Instruction set:  
Non-maskable interrupts: 2 sources  
Maskable interrupts:  
38 sources (µPD703201, 70F3201)  
39 sources (µPD703201Y, 70F3201Y)  
39 sources (µPD703204, 70F3204)  
40 sources (µPD703204Y, 70F3204Y)  
Software exceptions: 32 sources  
Exception trap: 1 source  
Signed multiplication, saturation operations, 32-bit  
shift instructions, bit manipulation instructions,  
load/store instructions  
{ Memory space:  
{ I/O lines Total: 82 (V850ES/SA2)  
102 (V850ES/SA3)  
64 MB linear address space  
Memory block division function:  
{ Timer/counters  
2 MB, 2 MB, 4 MB, 8 MB = Total four blocks  
{ External bus interface: 16-bit data bus  
Address bus: Separate output enabled  
{ Internal memory  
16-bit timer: 2 channels  
8-bit timer: 4 channels  
{ Real-time counter (for watch): 1 channel  
{ Watchdog timer: 1 channel  
Mask ROM:  
256 KB (µPD703201, 703201Y,  
703204, 703204Y)  
Flash memory: 256 KB (µPD70F3201, 70F3201Y,  
70F3204, 70F3204Y)  
RAM: 16 KB  
The information contained in this document is being issued in advance of the production cycle for the  
device. The parameters for the device may change before final production or NEC Corporation, at its own  
discretion, may withdraw the device prior to its production.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. U15436EJ1V0PM00 (1st edition)  
Date Published June 2001 N CP(K)  
Printed in Japan  
2001  
©

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