Datasheet > UPD46365364BF1-E33-EQ1

UPD46365364BF1-E33-EQ1

更新时间： 2024-11-14 06:28:23

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
39页	592K
描述
QDR SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

UPD46365364BF1-E33-EQ1 数据手册

浏览型号UPD46365364BF1-E33-EQ1的Datasheet PDF文件第2页

浏览型号UPD46365364BF1-E33-EQ1的Datasheet PDF文件第3页

浏览型号UPD46365364BF1-E33-EQ1的Datasheet PDF文件第4页

浏览型号UPD46365364BF1-E33-EQ1的Datasheet PDF文件第5页

浏览型号UPD46365364BF1-E33-EQ1的Datasheet PDF文件第6页

Datasheet

μPD46365084B

μPD46365094B

μPD46365184B

μPD46365364B

R10DS0090EJ0400

Rev.4.00

36M-BIT QDR^TMII SRAM

4-WORD BURST OPERATION

Nov 09 2012

Description

The μPD46365084B is a 4,194,304-word by 8-bit, the μPD46365094B is a 4,194,304-word by 9-bit, the

μPD46365184B is a 2,097,152-word by 18-bit and the μPD46365364B is a 1,048,576-word by 36-bit

synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-

transistor memory cell.

The μPD46365084B, μPD46365094B, μPD46365184B and μPD46365364B integrate unique synchronous

peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are

latched on the positive edge of K and K#. These products are suitable for application which require

synchronous operation, high speed, low voltage, high density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (13 x 15)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports with concurrent transactions

• 100% bus utilization DDR READ and WRITE operation

• Four-tick burst for reduced address frequency

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 3.3 ns (300 MHz) , 4.0 ns (250 MHz)

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

R10DS0090EJ0400 Rev.4.00

Nov 09, 2012

Page 1 of 38

12 3 4 5 6 7...39

中文翻译

下载PDF

与UPD46365364BF1-E33-EQ1相关器件

型号	品牌	获取价格	描述	数据表
UPD46365364BF1-E33-EQ1-A	RENESAS	获取价格	QDR SRAM
UPD46365364BF1-E33Y-EQ1	RENESAS	获取价格	QDR SRAM
UPD46365364BF1-E33Y-EQ1-A	RENESAS	获取价格	QDR SRAM
UPD46365364BF1-E40-EQ1	RENESAS	获取价格	QDRII/DDRII/ QDRII+/DDRII+ SRAM, LBGA, /Tray
UPD46365364BF1-E40-EQ1-A	RENESAS	获取价格	QDRII/DDRII/ QDRII+/DDRII+ SRAM, LBGA, /Tray
UPD464318ALS1-A4	ETC	获取价格	x18 Fast Synchronous SRAM
UPD464318ALS1-A44	ETC	获取价格	x18 Fast Synchronous SRAM
UPD464318ALS1-A5	ETC	获取价格	x18 Fast Synchronous SRAM
UPD464318LS1-A5	ETC	获取价格	x18 Fast Synchronous SRAM
UPD464318LS1-A6	ETC	获取价格	x18 Fast Synchronous SRAM