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UPD44321361GF-A75 PDF预览

UPD44321361GF-A75

更新时间: 2024-10-13 22:09:47
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日电电子 - NEC 静态存储器
页数 文件大小 规格书
24页 293K
描述
32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION

UPD44321361GF-A75 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD44321181, 44321361  
32M-BIT ZEROSB
TM
SRAM  
FLOW THROUGH OPERATION  
Description  
The µPD44321181 is a 2,097,152-word by 18-bit and the µPD44321361 is a 1,048,576-word by 36-bit ZEROSB  
static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The µPD44321181 and µPD44321361 are optimized to eliminate dead cycles for read to write, or write to read  
transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and  
output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input  
(CLK).  
The µPD44321181 and µPD44321361 are suitable for applications which require synchronous operation, high  
speed, low voltage, high density and wide bit configuration, such as buffer memory.  
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State  
(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes  
normal operation.  
The µPD44321181 and µPD44321361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness  
for high density and low capacitive loading.  
Features  
Low voltage core supply: VDD = 3.3 ± 0.165 V / 2.5 ± 0.125 V  
Synchronous operation  
100 percent bus utilization  
Internally self-timed write control  
Burst read / write : Interleaved burst and linear burst sequence  
Fully registered inputs and outputs for flow through operation  
All registers triggered off positive clock edge  
3.3V or 2.5V LVTTL Compatible : All inputs and outputs  
Fast clock access time : 7.5 ns (117 MHz)  
Asynchronous output enable : /G  
Burst sequence selectable : MODE  
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)  
Separate byte write enable : /BW1 to /BW4 (µPD44321361)  
/BW1 and /BW2 (µPD44321181)  
Three chip enables for easy depth expansion  
Common I/O using three state outputs  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with NEC Electronics sales  
representative for availability and additional information.  
The mark  
shows major revised points.  
Document No. M15958EJ5V0DS00 (5th edition)  
Date Published April 2005 NS CP(K)  
Printed in Japan  
2002, 2005  

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