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UPD44321361GF-A75Y-A PDF预览

UPD44321361GF-A75Y-A

更新时间: 2024-10-14 20:32:39
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器
页数 文件大小 规格书
24页 275K
描述
1MX36 ZBT SRAM, 7.5ns, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100

UPD44321361GF-A75Y-A 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.32.00.41风险等级:5.5
最长访问时间:7.5 ns其他特性:FLOW-THROUGH ARCHITECTURE; ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码:R-PQFP-G100JESD-609代码:e6
长度:20 mm内存密度:37748736 bit
内存集成电路类型:ZBT SRAM内存宽度:36
功能数量:1端子数量:100
字数:1048576 words字数代码:1000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:1MX36
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.7 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN BISMUTH端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

UPD44321361GF-A75Y-A 数据手册

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PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD44321181, 44321361  
32M-BIT ZEROSB
TM
SRAM  
FLOW THROUGH OPERATION  
Description  
The µPD44321181 is a 2,097,152-word by 18-bit and the µPD44321361 is a 1,048,576-word by 36-bit ZEROSB  
static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.  
The µPD44321181 and µPD44321361 are optimized to eliminate dead cycles for read to write, or write to read  
transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and  
output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input  
(CLK).  
The µPD44321181 and µPD44321361 are suitable for applications which require synchronous operation, high  
speed, low voltage, high density and wide bit configuration, such as buffer memory.  
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State  
(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes  
normal operation.  
The µPD44321181 and µPD44321361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness  
for high density and low capacitive loading.  
Features  
Low voltage core supply: VDD = 3.3 ± 0.165 V / 2.5 ± 0.125 V  
Synchronous operation  
Operating temperature : TA = 0 to 70 °C (-A75, -A85)  
TA = –40 to +85 °C (-A75Y, -A85Y)  
100 percent bus utilization  
Internally self-timed write control  
Burst read / write : Interleaved burst and linear burst sequence  
Fully registered inputs and outputs for flow through operation  
All registers triggered off positive clock edge  
3.3V or 2.5V LVTTL Compatible : All inputs and outputs  
Fast clock access time : 7.5 ns (117 MHz), 8.5 ns (100 MHz)  
Asynchronous output enable : /G  
Burst sequence selectable : MODE  
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)  
Separate byte write enable : /BW1 to /BW4 (µPD44321361)  
/BW1 and /BW2 (µPD44321181)  
Three chip enables for easy depth expansion  
Common I/O using three state outputs  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with NEC Electronics sales  
representative for availability and additional information.  
The mark  
shows major revised points.  
Document No. M15958EJ4V0DS00 (4th edition)  
Date Published November 2003 NS CP(K)  
Printed in Japan  
2002  

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