5秒后页面跳转
捷配首页

Datasheet > UPD44321362F1-C60-FQ2
UPD44321362F1-C60-FQ2 PDF预览

UPD44321362F1-C60-FQ2

更新时间： 2024-10-14 14:45:27
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟静态存储器内存集成电路
页数 文件大小 规格书
40页 738K
描述
1MX36 ZBT SRAM, 3.5ns, PBGA165, 15 X 17 MM, PLASTIC, FBGA-165

阅读下载

中文翻译

获取价格

UPD44321362F1-C60-FQ2 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991
HTS代码：8542.32.00.41风险等级：5.63
Is Samacsys：N最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：167 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：17 mm
内存密度：37748736 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：165字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5 V
认证状态：Not Qualified座面最大高度：1.4 mm
最大待机电流：0.06 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.36 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：15 mm
Base Number Matches：1

UPD44321362F1-C60-FQ2 数据手册

 浏览型号UPD44321362F1-C60-FQ2的Datasheet PDF文件第2页浏览型号UPD44321362F1-C60-FQ2的Datasheet PDF文件第3页浏览型号UPD44321362F1-C60-FQ2的Datasheet PDF文件第4页浏览型号UPD44321362F1-C60-FQ2的Datasheet PDF文件第5页浏览型号UPD44321362F1-C60-FQ2的Datasheet PDF文件第6页浏览型号UPD44321362F1-C60-FQ2的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD44321182, 44321322, 44321362  
32M-BIT ZEROSBTM SRAM  
PIPELINED OPERATION  
Description  
The µPD44321182 is a 2,097,152-word by 18-bit, the µPD44321322 is a 1,048,576-word by 32-bit and the  
µPD44321362 is a 1,048,576-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using  
full CMOS six-transistor memory cell.  
The µPD44321182, µPD44321322 and µPD44321362 are optimized to eliminate dead cycles for read to write, or  
write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst  
counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single  
clock input (CLK).  
The µPD44321182, µPD44321322 and µPD44321362 are suitable for applications which require synchronous  
operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.  
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).  
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal  
operation.  
The µPD44321182, µPD44321322 and µPD44321362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm  
package thickness or 165-pin PLASTIC FBGA for high density and low capacitive loading.  
Features  
• Low voltage core supply : VDD = 3.3 ± 0.165V (-A44, -A50, -A60, -A44Y, -A50Y, -A60Y)  
VDD = 2.5 ± 0.125V (-C50, -C60, -C50Y, -C60Y)  
• Synchronous operation  
• Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60, -C50, -C60)  
TA = –40 to +85 °C (-A44Y, -A50Y, -A60Y, -C50Y, -C60Y)  
• 100 percent bus utilization  
• Internally self-timed write control  
• Burst read / write : Interleaved burst and linear burst sequence  
• Fully registered inputs and outputs for pipelined operation  
• All registers triggered off positive clock edge  
• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs  
• Fast clock access time : 2.8 ns (225 MHz), 3.2 ns (200 MHz), 3.5 ns (167 MHz)  
• Asynchronous output enable : /G  
• Burst sequence selectable : MODE  
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)  
• Separate byte write enable : /BW1 to /BW4 (µPD44321322 and µPD44321362)  
/BW1 and /BW2 (µPD44321182)  
• Three chip enables for easy depth expansion  
• Common I/O using three state outputs  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with NEC Electronics sales  
representative for availability and additional information.  
The mark  
shows major revised points.  
Document No. M16024EJ1V0DS00 (1st edition)  
Date Published December 2002 NS CP(K)  
Printed in Japan  
2002  
1234567...40

中文翻译

下载PDF

与UPD44321362F1-C60-FQ2相关器件

型号 品牌 获取价格 描述 数据表
UPD44321362GF-A44-A RENESAS

获取价格

 		ZBT SRAM, 1MX36, 2.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD44321362GF-A44Y RENESAS

获取价格

 		ZBT SRAM, 1MX36, 2.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD44321362GF-A44Y-A RENESAS

获取价格

 		ZBT SRAM, 1MX36, 2.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD44321362GF-A50 NEC

获取价格

 		32M-BIT ZEROSB SRAM PIPELINED OPERATIO
UPD44321362GF-A50-A NEC

获取价格

 		ZBT SRAM, 1MX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD44321362GF-A50Y RENESAS

获取价格

 		1MX36 ZBT SRAM, 3.2ns, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD44321362GF-A50Y NEC

获取价格

 		ZBT SRAM, 1MX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD44321362GF-A50Y-A NEC

获取价格

 		暂无描述
UPD44321362GF-A60Y-A RENESAS

获取价格

 		1MX36 ZBT SRAM, 3.5ns, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100
UPD44321362GF-C50 RENESAS

获取价格

 		ZBT SRAM, 1MX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100

与UPD44321362F1-C60-FQ2相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证