Datasheet > UPD4382362GF-A67

UPD4382362GF-A67

更新时间： 2024-09-15 23:40:15

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器时钟
页数	文件大小	规格书
24页	211K
描述
x36 Fast Synchronous SRAM

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UPD4382362GF-A67 数据手册

DATA SHEET

MOS INTEGRATED CIRCUIT

PD4382162, 4382182, 4382322, 4382362

8M-BIT CMOS SYNCHRONOUS FAST SRAM

PIPELINED OPERATION

SINGLE CYCLE DESELECT

Description

The µPD4382162 is a 524,288-word by 16-bit, the µPD4382182 is a 524,288-word by 18-bit, µPD4382322 is a 262,144-

word by 32-bit and the µPD4382362 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS

technology using N-channel four-transistor memory cell.

The µPD4382162, µPD4382182, µPD4382322 and µPD4382362 integrates unique synchronous peripheral circuitry, 2-

bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single

clock input (CLK).

The µPD4382162, µPD4382182, µPD4382322 and µPD4382362 are suitable for applications which require synchronous

operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In

the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.

The µPD4382162, µPD4382182, µPD4382322 and µPD4382362 are packaged in 100-pin plastic LQFP with a 1.4 mm

package thickness for high density and low capacitive loading.

Features

• 3.3 V (Chip) / 3.3 V or 2.5 V (I/O) Supply

• Synchronous operation

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs and outputs for pipelined operation

• Single-Cycle deselect timing

• All registers triggered off positive clock edge

• 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs

• Fast clock access time :

★

3.8 ns (150 MHz), 4.0 ns (133 MHz) (µPD4382322, µPD4382362), 4.0 ns (133 MHz) (µPD4382162, µPD4382182)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable :

/BW1 - /BW4 (µPD4382322, µPD4382362), /BW1 - /BW2 (µPD4382162, µPD4382182), /BWE

Global write enable : /GW

• Three chip enables for easy depth expansion

• Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M14020EJ5V0DS00 (5th edition)

Date Published January 2000 NS CP(K)

Printed in Japan

The mark shows major revised points.

★

1999

12 3 4 5 6 7...24

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与UPD4382362GF-A67相关器件

型号	品牌	获取价格	描述	数据表
UPD4382362GF-A67B	ETC	获取价格	x36 Fast Synchronous SRAM
UPD4382362GF-A75	ETC	获取价格	x36 Fast Synchronous SRAM
UPD4382362GF-A75B	ETC	获取价格	x36 Fast Synchronous SRAM
UPD4382363GF-A67	ETC	获取价格	x36 Fast Synchronous SRAM
UPD4382363GF-A75	ETC	获取价格	x36 Fast Synchronous SRAM
UPD4383362GF-A75	NEC	获取价格	Cache SRAM, 256KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100
UPD44008LLE-A12	NEC	获取价格	Standard SRAM, 512KX8, 12ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36
UPD441000LF1-BA1-B10X	ETC	获取价格	x8 SRAM
UPD441000LF1-BA1-B70X	ETC	获取价格	x8 SRAM
UPD441000LF1-BA1-B85X	ETC	获取价格	x8 SRAM

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