DATA SHEET
MOS INTEGRATED CIRCUIT
µPD17072,17073
4-BIT SINGLE-CHIP MICROCONTROLLER
WITH HARDWARE FOR DIGITAL TUNING SYSTEM
DESCRIPTION
µPD17072 and 17073 are low-voltage 4-bit single-chip CMOS microcontrollers containing hardware ideal for
organizing a digital tuning system.
The CPU employs 17K architecture and can manipulate the data memory directly, perform arithmetic operations,
and control peripheral hardware with a single instruction. All the instructions are 16-bit one-word instructions.
As peripheral hardware, a prescaler that can operate at up to 230 MHz for a digital tuning system, a PLL frequency
synthesizer, and an intermediate frequency (IF) counter are integrated in addition to I/O ports, an LCD controller/driver,
A/D converter, and BEEP.
Therefore, a high-performance, multi-function digital tuning system can be configured with a single chip of
µPD17072 or 17073.
Because the µPD17072 and 17073 can operate at low voltage (VDD = 1.8 to 3.6 V), they are ideal for controlling
battery-cell driven portable devices such as portable radio equipment, headphone stereos, or radio cassette
recorders.
FEATURES
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17K architecture: general-purpose register system
Program memory (ROM)
6 KB (3072 × 16 bits): µPD17072
8 KB (4096 × 16 bits): µPD17073
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General-purpose data memory (RAM)
176 × 4 bits
Instruction execution time
53.3 µs (with 75-kHz crystal resonator: normal operation)
106.6 µs (with 75-kHz crystal resonator: low-speed mode)
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Decimal operation
Table reference
Hardware for PLL frequency synthesizer
Dual modulus prescaler (230 MHz max.), programmable divider, phase comparator, charge pump
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Various peripheral hardware
General-purpose I/O ports, LCD controller/driver, serial interface, A/D converter, BEEP, intermediate frequency
(IF) counter
Many interrupts
External: 1 channel
Internal: 2 channels
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Power-ON reset, CE reset, and power failure detector
CMOS low power consumption
Supply voltage: VDD = 1.8 to 3.6 V
Unless otherwise stated, the µPD17073 is taken as a representative product in this document.
The information in this document is subject to change without notice.
Document No. U11450EJ1V0DS00 (1st edition)
Date Published September 1996 P
Printed in Japan
1996
©