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UPD160010N-XXX PDF预览

UPD160010N-XXX

更新时间: 2024-09-13 04:26:51
品牌 Logo 应用领域
日电电子 - NEC 驱动器输出元件
页数 文件大小 规格书
19页 318K
描述
384-/360-OUTPUT TFT-LCD SOURCE DRIVER

UPD160010N-XXX 技术参数

生命周期:Obsolete包装说明:TCP
Reach Compliance Code:unknown风险等级:5.84
数据输入模式:SERIAL接口集成电路类型:LIQUID CRYSTAL DISPLAY DRIVER
JESD-30 代码:X-XUUC-N复用显示功能:NO
功能数量:1区段数:384
最高工作温度:90 °C最低工作温度:-10 °C
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
认证状态:Not Qualified最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3 V
电源电压1-最大:16.5 V电源电压1-分钟:10 V
电源电压1-Nom:15.4 V表面贴装:YES
温度等级:OTHER端子形式:NO LEAD
端子位置:UPPERBase Number Matches:1

UPD160010N-XXX 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD160010  
384-/360-OUTPUT TFT-LCD SOURCE DRIVER  
(COMPATIBLE WITH 256 GRAY SCALES, mini-LVDS INTERFACE SUPPORTED)  
DESCRIPTION  
The µ PD160010 is a source driver for TFT-LCDS that supports the display of 256 gray scales and employs mini-LVDS  
interface. Which can realize a full-color display of 16,777,216 colors by output of 256 values γ -corrected by an internal D/A  
converter and 10-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.2 V to VDD2 0.2  
V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line  
inversion, n-line inversion, this source driver is equipped with a built-in 8-bit D/A converter circuit whose odd output pins and  
even output pins respectively output gray scale voltages of differing polarity. Because of the incorporation of mini-LVDS  
interface, the data transfer speed has improved and the amount of wiring on the PCB has been significantly reduced.  
Remark "mini-LVDS" is the technology with Texas Instruments applied LVDS technology and developed.  
(LVDS: Low Voltage Differential Signaling)  
FEATURES  
Differential interface: CLK, gray scale data,  
CMOS interface: STHR(L), R,/L, STB, SB, POL, Osel, Vsel1, Vsel2, SRC, ORC, RxBIAS1, RxBIAS2  
384/360 outputs (Osel)  
Capable of outputting 256 values by means of 10-by-2 external power modules (20 units) and a D/A converter  
Logic power supply voltage (VDD1): 2.7 to 3.6V  
Driver power supply voltage (VDD2): 10.0 to 16.5V  
High-speed data transfer: fCLK = 190 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V)  
Output dynamic range: VSS2 + 0.2 V to VDD2 0.2 V  
Apply for dot-line inversion, n-line inversion  
Output voltage polarity inversion function (POL)  
ORDERING INFORMATION  
Part Number  
Package  
µPD160010N-xxx  
µPD160010NL-xxx  
TCP (TAB package)  
COF (COF package)  
Remark The TCP/COF’s external shape is customized. To order the required shape, please contact one of our sales  
representatives.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No.  
S16316EJ2V0DS00 (2nd edition)  
The mark shows major revised points.  
2003  
Date Published March 2004 NS CP (K)  
Printed in Japan  

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