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UPA1560H-AZ PDF预览

UPA1560H-AZ

更新时间: 2024-10-30 20:56:19
品牌 Logo 应用领域
日电电子 - NEC 局域网开关脉冲晶体管
页数 文件大小 规格书
8页 73K
描述
Power Field-Effect Transistor, 3A I(D), 120V, 0.2ohm, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SIP-10

UPA1560H-AZ 技术参数

生命周期:Obsolete包装说明:FLANGE MOUNT, R-PSFM-T10
针数:10Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8541.29.00.95
风险等级:5.83雪崩能效等级(Eas):0.9 mJ
外壳连接:ISOLATED配置:2 BANKS, COMMON SOURCE, 2 ELEMENTS WITH BUILT-IN DIODE
最小漏源击穿电压:120 V最大漏极电流 (ID):3 A
最大漏源导通电阻:0.2 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-30 代码:R-PSFM-T10元件数量:2
端子数量:10工作模式:ENHANCEMENT MODE
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:FLANGE MOUNT峰值回流温度(摄氏度):NOT SPECIFIED
极性/信道类型:N-CHANNEL最大脉冲漏极电流 (IDM):12 A
认证状态:Not Qualified表面贴装:NO
端子形式:THROUGH-HOLE端子位置:SINGLE
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

UPA1560H-AZ 数据手册

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DATA SHEET  
COMPOUND FIELD EFFECT POWER TRANSISTOR  
µ PA1560  
N-CHANNEL POWER MOS FET ARRAY  
SWITCHING  
INDUSTRIAL USE  
DESCRIPTION  
PACKAGE DRAWING (Unit : mm)  
The µPA1560 is N-Channel PowerMOS FET Array  
that built in 4 circuits designed for solenoid, motor and  
lamp driver.  
4.0  
26.8 MAX.  
FEATURES  
Full mold package with 4 circuits  
4 V driving is possible  
Low on-state resistance  
1.4  
0.5±0.1  
2.54  
RDS(on)1 = 165 mMAX. (VGS = 10 V, ID = 1.5 A)  
RDS(on)2 = 200 mMAX. (VGS = 4 V, ID = 1.5 A)  
Low input capacitance  
1.4 0.6±0.1  
Ciss = 600 pF TYP.  
1 2 3 4 5 6 7 8 910  
ORDERING INFORMATION  
EQUIVALENT CIRCUIT  
PART NUMBER  
PACKAGE  
10-pin SIP  
µ PA1560H  
3
5
7
9
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)  
2
1
4
6
8
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC) (TC = 25°C)  
Drain Current (pulse) Note1  
VDSS  
VGSS(AC)  
VGSS(DC)  
ID(DC)  
ID(pulse)  
PT1  
120  
±20  
V
V
10  
+ 20, –10  
±3.0  
±12  
V
ELECTRODE CONNECTION  
2, 4, 6, 8 : Gate  
A
A
3, 5, 7, 9 : Drain  
Total Power Dissipation (TC = 25°C)  
Total Power Dissipation (TA = 25°C)  
Channel Temperature  
28  
W
W
°C  
1, 10  
: Source  
PT2  
3.7  
Tch  
150  
Storage Temperature  
Tstg  
–55 to + 150 °C  
Single Avalanche Current Note2  
Single Avalanche Energy Note2  
IAS  
3.0  
0.9  
A
EAS  
mJ  
Notes 1. PW 10 µs, Duty Cycle 1 %  
2. Starting Tch = 25 °C, VDD = 60 V, RG = 25 , VGS = 20 V0V  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When  
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated  
voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No.  
Date Published April 2001 NS CP(K)  
Printed in Japan  
G14283EJ2V0DS00 (2nd edition)  
1999  
©
The mark shows major revised points.  

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