5秒后页面跳转
捷配首页

Datasheet > UCLXT315ANE.A2
UCLXT315ANE.A2 PDF预览

UCLXT315ANE.A2

更新时间： 2024-09-15 19:48:55
品牌 Logo 应用领域
英特尔 - INTEL 光电二极管
页数 文件大小 规格书
352页 2371K
描述
Digital Transmission Interface, T-1(DS1), CMOS, PDIP16

阅读下载

中文翻译

获取价格

UCLXT315ANE.A2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
风险等级：5.92运营商类型：T-1(DS1)
数据速率：1544 MbpsJESD-30 代码：R-PDIP-T16
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5 V认证状态：Not Qualified
子类别：Digital Transmission Interfaces最大压摆率：23 mA
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

UCLXT315ANE.A2 数据手册

 浏览型号UCLXT315ANE.A2的Datasheet PDF文件第2页浏览型号UCLXT315ANE.A2的Datasheet PDF文件第3页浏览型号UCLXT315ANE.A2的Datasheet PDF文件第4页浏览型号UCLXT315ANE.A2的Datasheet PDF文件第5页浏览型号UCLXT315ANE.A2的Datasheet PDF文件第6页浏览型号UCLXT315ANE.A2的Datasheet PDF文件第7页 
Intel® IXF6048  
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface  
Datasheet  
Intel IXF6048 is a single-chip interface solution for the transport of ATM cells or HDLC frames over  
SONET/SDH. Intel IXF6048 can operate as a quad 51/155/622 Mbit/s or as a single 2488 Mbit/s  
SONET/SDH processor. When configured in ATM UNI mode, it interfaces with an ATM layer  
device using the industry standard UTOPIA interface (Levels 3/2/1). When configured in Packet Over  
SONET mode, it transfers the PPP frames using a UTOPIA-enhanced interface, based on the ATM  
industry standard UTOPIA, which supports the transfer of variable length frames.  
Product Features  
■ Supports the UTOPIA Level 3 (single 64-  
Applications  
bit, 32-bit, or quad 8-bit), Level 2 (single 8/  
16-bit), and Level 1 (quad 8/16-bit)  
■ WAN and edge ATM switches  
interface modes.  
■ Layer 3 switches  
■ Implements a GFC halt function (ITU I.150  
■ Video and File Servers  
and I.361).  
■ Broadband Switching Systems  
■ Handles full J0/J1 trace identifier  
processing.  
Features  
■ SOH, POH and Alarm insertion/extraction  
ports.  
■ Maps ATM cells or HDLC frames into one  
STS-48c/STM-16c/STS-48/STM-16/STM-  
4 or four STS-12c/STM-4c/STS-3c/STM-  
1/STS-1 SONET/SDH signals.  
■ In POS mode, each channel performs SPE  
scrambling (1 + X43), HDLC processing,  
and offers a UTOPIA-type FIFO-based  
POS interface.  
■ Hardware assistance for APS  
implementation, via K1 and K2 bytes.  
■ Provides a 16-bit microprocessor port.  
One-second counters for B1/B2/B3, M1/G1  
REI, etc.  
■ 600 TBGA package; -40 °C to +85 °C  
operating conditions; low power, 3.3 V  
operation, 5 V tolerant I/O  
Figure 1. Block Diagram  
SOH / POH / Alarms Extraction Ports  
IXF6048  
channel  
#3  
channel  
Receive ATM/POS  
#2  
channel  
#1  
Level 1/2/3 UTOPIA  
Interface  
channel  
Rx UTOPIA  
64-bit X 1  
32-bit X 1  
16-bit X 1  
8-bit X 1  
16-bit X 4  
or  
Rx Line Interface  
SONET/  
#0  
PECL 16-bit X 1  
PECL 1-bit X 4  
TTL 32-bit X 1  
TTL 8-bit X 4  
TTL 1-bit X 4  
Receive  
Serial to  
Parallel  
Interface  
(RSPI)  
#
3
SDH  
DEMUX  
(non conca-  
tenated  
Receive  
32 or 2K  
Receive  
Regenera-tor  
Section  
Receive  
Multiplex  
Section  
#
#
Receive  
High-Order  
Path  
Processor  
(RHPP)  
POS Controller  
(RPOSC)  
32 or 2K  
32 or 2K  
2
1
#
0
256-cell (ATM)  
16 KB (POS)  
FIFO  
Receive  
ATM Cell Processor  
(RACP)  
Processor  
(RRSP)  
Processor  
(RMSP)  
modes)  
8-bit X 4  
Section  
Trace  
Path  
Trace  
Buffer  
Transmit ATM/POS  
Level 1/2/3 UTOPIA  
Interface  
Buffer  
Tx UTOPIA  
64-bit X 1  
32-bit X 1  
16-bit X 1  
8-bit X 1  
16-bit X 4  
or  
Tx Line Interface  
PECL 16-bit X 1  
PECL 1-bit X 4  
TTL 32-bit X 1  
TTL 8-bit X 4  
SONET/  
SDH  
Transmit  
Parallel to  
Serial  
Interface  
(TPSI)  
Transmit  
ATM Cell Processor  
(TACP)  
#
3
32 or 2K  
Transmit  
Regenera-tor  
Section  
Transmit  
Multiplex  
Section  
Transmit  
High-Order  
Path  
Processor  
(THPP)  
#
MUX  
32 or 2K  
32 or 2K  
2
#
(non conca-  
tenated  
modes)  
1
#
0
256-cell (ATM)  
16 KB (POS)  
FIFO  
Transmit  
POS Controller  
(TPOSC)  
Processor  
(TRSP)  
Processor  
(TMSP)  
TTL 1-bit X 4  
8-bit X 4  
Microprocessor Interface  
16bit, Intel/Motorola selectable  
(MPI)  
JTAG  
Interface  
JTAG Test  
Access Port  
µP lines  
SOH / POH / Alarms Insertion Ports  
Order Number: 273644-004  
September 2003  
 
 
1234567...352

中文翻译

下载PDF

与UCLXT315ANE.A2相关器件

型号 品牌 获取价格 描述 数据表
UCLXT315ANEA2 INTEL

获取价格

 		PCM Transceiver, 1-Func, CMOS, PDIP16, ROHS COMPLIANT, PLASTIC, DIP-16
UCM0J101MCL1GS NICHICON

获取价格

 		UCM
UCM0J152MNL1GS NICHICON

获取价格

 		UCM
UCM0J152MNS1GS NICHICON

获取价格

 		UCM
UCM0J221MCL1GS NICHICON

获取价格

 		UCM
UCM0J222MNL1GS NICHICON

获取价格

 		UCM
UCM0J331MCL1GS NICHICON

获取价格

 		UCM
UCM0J471MCL1GS NICHICON

获取价格

 		UCM
UCM0J471MCS1GS NICHICON

获取价格

 		UCM
UCM0J681MCL1GS NICHICON

获取价格

 		UCM

与UCLXT315ANE.A2相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证