Datasheet > UC2874QTR-1

UC2874QTR-1

更新时间： 2024-11-01 23:38:55

品牌	Logo	应用领域
其他 - ETC		开关控制器
页数	文件大小	规格书
10页	442K
描述
Current-Mode SMPS Controller

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中文翻译

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数据手册

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UC2874QTR-1 数据手册

UC1874-1,-2

UC2874-1,-2

UC3874-1,-2

High Efficiency, Synchronous, Step-down (Buck) Controllers

FEATURES

DESCRIPTION

Not Recommended for New Designs.

•

Operation to 36V Input Voltage

The UC3874 family of synchronous step-down (Buck) regulators provides

high efficiency power conversion from an input voltage range of 4.5 to 36

volts. The UC3874 is tailored for battery powered applications such as

laptop computers, consumer products, communications systems, and

aerospace which demand high performance and long battery life. The

synchronous regulator replaces the catch diode in the standard buck

regulator with a low Rds(on) N-channel MOSFET switch allowing for

significant efficiency improvements. The high side N-channel MOSFET

switch is driven out of phase from the low side N-channel MOSFET switch

by an on-chip bootstrap circuit which requires only a single external

capacitor to develop the regulated gate drive. Fixed frequency, average

current mode control provides the regulator with inherent slope

compensation, tight regulation of the output voltage, and superior load and

line transient response. Switching frequencies up to 300kHz are possible.

•

Fixed Frequency Average Current

Mode Control

•

Standby Mode for Improved

Efficiency at Light Load

Drives External N-Channel

MOSFETs for Highest Efficiency

•

Sleep Mode Current < 50mA

Complementary 1 Amp Outputs with

Regulated Gate Drive Voltage

•

LDO (Low Drop Out) Virtual 100%

Duty Cycle Operation

Light load efficiency is improved by a fully programmable standby mode, in

which the quiescent current consumption of the controller is significantly re-

duced. The reduction is achieved by disabling the MOSFET driver outputs

and the internal oscillator when the controller has sensed that the the out-

put load current has dropped a user programmable amount from full load.

Non-Overlapping Gate Drives

(continued)

BLOCK DIAGRAM

UDG-95005-1

2/98

12 3 4 5 6 7...10

中文翻译

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