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SGLS233A − FEBRUARY 2004 − REVISED DECEMBER 2008
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
D
Low Startup Current −150 mA
Outputs Active Low During UVLO
Soft-Start Control
D
D
D
D
D
D
D
Extended Temperature Performance of
−25°C to 110°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Latched Over-Current Comparator With Full
Cycle Restart
D
Trimmed Reference
Enhanced Product Change Notification
DW PACKAGE
(TOP VIEW)
†
Qualification Pedigree
Zero to 100% Duty Cycle Control
VREF
E/AOUT
EA−
GND
1
28
27
26
25
24
23
22
21
20
19
18
RAMP
Programmable Output Turn-On Delay
2
SLOPE
CLOCKSYNC
FREQSET
DELAYSET A−B
GND
3
Compatible with Voltage or Current Mode
Topologies
EA+
4
CS+
5
D
Practical Operation at Switching
Frequencies to 1 MHz
SOFTSTART
6
GND
GND
7
D
D
D
Four 2 A Totem Pole Outputs
10 MHz Error Amplifier
Under-Voltage Lockout
GND
8
GND
GND
9
DELAYSET C−D
NC
NC
10
11
†
OUTA
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
OUTD 12
OUTC 13
VC 14
17 OUTB
16 PWRGND
15 VIN
NC = No Connect
description/ordering information
The UC2875 integrated circuit implements control of a bridge power stage by phase-shifting the switching of
one half-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination
with resonant, zero-voltage switching for high efficiency performance at high frequencies. This circuit may be
configured to provide control in either voltage or current mode operation, with a separate over-current shutdown
for fast fault protection.
A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay,
providing time to allow the resonant switching action, is independently controllable for each output pair (A−B,
C−D).
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
A
PACKAGE
−25°C to 110°C
SOP − DW Tape and reel
UC2875SDWREP
UC2875SEP
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004 − 2008 Texas Instruments Incorporated
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1
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