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UC2874J-2 PDF预览

UC2874J-2

更新时间： 2024-11-20 22:16:11
品牌 Logo 应用领域
德州仪器 - TI 稳压器开关式稳压器或控制器电源电路开关式控制器
页数 文件大小 规格书
10页 352K
描述
High Efficiency, Synchronous, Step-down Buck Controllers

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中文翻译

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UC2874J-2 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP18,.3针数：18
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.71
模拟集成电路 - 其他类型：SWITCHING CONTROLLER控制模式：CURRENT-MODE
控制技术：PULSE WIDTH MODULATION最大输入电压：24 V
最小输入电压：12 V标称输入电压：12 V
JESD-30 代码：R-GDIP-T18功能数量：1
端子数量：18最高工作温度：85 °C
最低工作温度：-25 °C最大输出电流：1 A
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP18,.3封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Switching Regulator or Controllers
表面贴装：NO切换器配置：PUSH-PULL
最大切换频率：300 kHz技术：BIPOLAR
温度等级：OTHER端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

UC2874J-2 数据手册

 浏览型号UC2874J-2的Datasheet PDF文件第2页浏览型号UC2874J-2的Datasheet PDF文件第3页浏览型号UC2874J-2的Datasheet PDF文件第4页浏览型号UC2874J-2的Datasheet PDF文件第5页浏览型号UC2874J-2的Datasheet PDF文件第6页浏览型号UC2874J-2的Datasheet PDF文件第7页 
UC1874-1,-2  
UC2874-1,-2  
UC3874-1,-2  
High Efficiency, Synchronous, Step-down (Buck) Controllers  
FEATURES  
DESCRIPTION  
•
Operation to 36V Input Voltage  
The UC3874 family of synchronous step-down (Buck) regulators provides  
high efficiency power conversion from an input voltage range of 4.5 to 36  
volts. The UC3874 is tailored for battery powered applications such as  
laptop computers, consumer products, communications systems, and  
aerospace which demand high performance and long battery life. The  
synchronous regulator replaces the catch diode in the standard buck  
regulator with a low Rds(on) N-channel MOSFET switch allowing for  
significant efficiency improvements. The high side N-channel MOSFET  
switch is driven out of phase from the low side N-channel MOSFET switch  
by an on-chip bootstrap circuit which requires only a single external  
capacitor to develop the regulated gate drive. Fixed frequency, average  
current mode control provides the regulator with inherent slope  
compensation, tight regulation of the output voltage, and superior load and  
line transient response. Switching frequencies up to 300kHz are possible.  
•
Fixed Frequency Average Current  
Mode Control  
•
•
Standby Mode for Improved  
Efficiency at Light Load  
Drives External N-Channel  
MOSFETs for Highest Efficiency  
•
•
Sleep Mode Current < 50mA  
Complementary 1 Amp Outputs with  
Regulated Gate Drive Voltage  
•
•
LDO (Low Drop Out) Virtual 100%  
Duty Cycle Operation  
Light load efficiency is improved by a fully programmable standby mode, in  
which the quiescent current consumption of the controller is significantly re-  
duced. The reduction is achieved by disabling the MOSFET driver outputs  
and the internal oscillator when the controller has sensed that the the out-  
put load current has dropped a user programmable amount from full load.  
Non-Overlapping Gate Drives  
(continued)  
BLOCK DIAGRAM  
UDG-95005-1  
SLUS286A - FEBRUARY 1998 - REVISED OCTOBER 2001  
1234567...10

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