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UC1527AN

更新时间: 2024-11-05 03:57:27
品牌 Logo 应用领域
德州仪器 - TI 脉冲
页数 文件大小 规格书
9页 440K
描述
Regulating Pulse Width Modulators

UC1527AN 数据手册

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UC1525A/27A  
UC2525A/27A  
UC3525A/27A  
Regulating Pulse Width Modulators  
FEATURES  
DESCRIPTION  
8 to 35V Operation  
The UC1525A/1527A series of pulse width modulator integrated circuits are de-  
signed to offer improved performance and lowered external parts count when  
used in designing all types of switching power supplies. The on-chip +5.1V ref-  
erence is trimmed to ±1% and the input common-mode range of the error ampli-  
fier includes the reference voltage, eliminating external resistors. A sync input to  
the oscillator allows multiple units to be slaved or a single unit to be synchro-  
nized to an external system clock. A single resistor between the CT and the dis-  
charge terminals provides a wide range of dead-time adjustment. These  
devices also feature built-in soft-start circuitry with only an external timing ca-  
pacitor required. A shutdown terminal controls both the soft-start circuitry and  
the output stages, providing instantaneous turn off through the PWM latch with  
pulsed shutdown, as well as soft-start recycle with longer shutdown commands.  
These functions are also controlled by an undervoltage lockout which keeps the  
outputs off and the soft-start capacitor discharged for sub-normal input volt-  
ages. This lockout circuitry includes approximately 500mV of hysteresis for jit-  
ter-free operation. Another feature of these PWM circuits is a latch following the  
comparator. Once a PWM pulse has been terminated for any reason, the out-  
puts will remain off for the duration of the period. The latch is reset with each  
clock pulse. The output stages are totem-pole designs capable of sourcing or  
sinking in excess of 200mA. The UC1525A output stage features NOR logic,  
giving a LOW output for an OFF state. The UC1527A utilizes OR logic which  
results in a HIGH output level when OFF.  
5.1V Reference Trimmed to ±1%  
100Hz to 500kHz Oscillator Range  
Separate Oscillator Sync Terminal  
Adjustable Deadtime Control  
Internal Soft-Start  
Pulse-by-Pulse Shutdown  
Input Undervoltage Lockout with  
Hysteresis  
Latching PWM to Prevent Multiple  
Pulses  
Dual Source/Sink Output Drivers  
BLOCK DIAGRAM  
OSC  
OUT  
VREF  
16  
4
13  
11  
VC  
NOR  
UVLO  
Lockout  
Reference  
Regulator  
+VIN 15  
OUTPUT A  
GROUND 12  
To internal  
circuitry  
SYNC  
RT  
3
6
5
7
Flip  
Flop  
NOR  
OSC  
CT  
14  
OUTPUT B  
DISCHARGE  
UC1525A Output Stage  
13  
11  
VC  
COMP  
R
S
S
OR  
COMPENSATION  
INV INPUT  
9
1
2
8
PWM  
La tch  
Error  
Amp  
VREF  
50 µA  
OUTPUT A  
NI INPUT  
SOFTSTART  
OR  
3 kΩ  
SHUTDOWN 10  
14  
OUTPUT B  
5 kΩ  
UC1527A Output Stage  
SLUS191B - February 1997 - Revised June 2005  

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