Datasheet > U62H256AS2A35LL

U62H256AS2A35LL

更新时间： 2024-11-05 05:53:31

品牌	Logo	应用领域
ZMD		静态存储器
页数	文件大小	规格书
10页	162K
描述
AUTOMOTIVE FAST 32K X 8 SRAM

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U62H256AS2A35LL 数据手册

U62H256A

Automotive Fast 32K x 8 SRAM

Features

Description

! 32768 x 8 bit static CMOS RAM

! 35 and 55 ns Access Time

! Common data inputs and

data outputs

The U62H256A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

go High-Z until the new information

is available. The data outputs have

no preferred state. The Read cycle

is finished by the falling edge of W,

or by the rising edge of E, respec-

tively.

! Three-state outputs

! Typ. operating supply current

35 ns: 45 mA

- Read

- Write

- Standby

- Data Retention

The memory array is based on a

6-transistor cell.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

55 ns: 30 mA

! Standby current < 50 µA at 125 °C The circuit is activated by the fal-

! TTL/CMOS-compatible

! Power supply voltage 5 V

! Operating temperature range

-40 °C to 85 °C

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word will be available at the

outputs DQ0-DQ7. After the

address change, the data outputs

-40 °C to 125 °C

! QS 9000 Quality Standard

! ESD protection > 2000 V

(MIL STD 883C M3015.7)

! Latch-up immunity >100 mA

! Package: SOP28 (300/330 mil)

Pin Configuration

Pin Description

VCC

A14

A12

A13

Signal Name Signal Description

A0 - A14

Address Inputs

DQ0 - DQ7

Data In/Out

A11

Chip Enable

Output Enable

Write Enable

Power Supply Voltage

Ground

VCC

SOP

A10

DQ7

VSS

DQ0

DQ1

DQ2

VSS

DQ6

DQ5

DQ4

DQ3

Top View

April 20, 2004

12 3 4 5 6 7...10

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