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U62H256ASA35 PDF预览

U62H256ASA35

更新时间: 2024-02-04 23:35:29
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
10页 162K
描述
Standard SRAM, 32KX8, 35ns, CMOS, PDSO28, 0.300 INCH, SOP-28

U62H256ASA35 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.69
最长访问时间:35 nsJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:17.9 mm
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

U62H256ASA35 数据手册

 浏览型号U62H256ASA35的Datasheet PDF文件第2页浏览型号U62H256ASA35的Datasheet PDF文件第3页浏览型号U62H256ASA35的Datasheet PDF文件第4页浏览型号U62H256ASA35的Datasheet PDF文件第5页浏览型号U62H256ASA35的Datasheet PDF文件第6页浏览型号U62H256ASA35的Datasheet PDF文件第7页 
U62H256A  
Automotive Fast 32K x 8 SRAM  
Features  
Description  
! 32768 x 8 bit static CMOS RAM  
! 35 and 55 ns Access Time  
! Common data inputs and  
data outputs  
The U62H256A is a static RAM  
manufactured using a CMOS pro-  
cess technology with the following  
operating modes:  
go High-Z until the new information  
is available. The data outputs have  
no preferred state. The Read cycle  
is finished by the falling edge of W,  
or by the rising edge of E, respec-  
tively.  
! Three-state outputs  
! Typ. operating supply current  
35 ns: 45 mA  
- Read  
- Write  
- Standby  
- Data Retention  
The memory array is based on a  
6-transistor cell.  
Data retention is guaranteed down  
to 2 V. With the exception of E, all  
inputs consist of NOR gates, so  
that no pull-up/pull-down resistors  
are required.  
55 ns: 30 mA  
! Standby current < 50 µA at 125 °C The circuit is activated by the fal-  
! TTL/CMOS-compatible  
! Power supply voltage 5 V  
! Operating temperature range  
-40 °C to 85 °C  
ling edge of E. The address and  
control inputs open simultaneously.  
According to the information of W  
and G, the data inputs, or outputs,  
are active. In a Read cycle, the  
data outputs are activated by the  
falling edge of G, afterwards the  
data word will be available at the  
outputs DQ0-DQ7. After the  
address change, the data outputs  
-40 °C to 125 °C  
! QS 9000 Quality Standard  
! ESD protection > 2000 V  
(MIL STD 883C M3015.7)  
! Latch-up immunity >100 mA  
! Package: SOP28 (300/330 mil)  
Pin Configuration  
Pin Description  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
A14  
A12  
A7  
2
W
3
A13  
A8  
Signal Name Signal Description  
A6  
4
A5  
5
A9  
A0 - A14  
Address Inputs  
DQ0 - DQ7  
Data In/Out  
A4  
6
A11  
Chip Enable  
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
E
G
W
VCC  
A3  
7
G
SOP  
A2  
8
A10  
A1  
9
E
DQ7  
A0  
10  
11  
12  
13  
14  
VSS  
DQ0  
DQ1  
DQ2  
VSS  
DQ6  
DQ5  
DQ4  
DQ3  
Top View  
April 20, 2004  
1

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