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TTMM54C175J/883 PDF预览

TTMM54C175J/883

更新时间: 2024-11-03 09:46:07
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路触发器
页数 文件大小 规格书
6页 106K
描述
D Flip-Flop, 4-Func, Positive Edge Triggered, CMOS, CDIP16

TTMM54C175J/883 数据手册

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February 1988  
MM54C175/MM74C175 Quad D Flip-Flop  
General Description  
The MM54C175/MM74C175 consists of four positive-edge  
All inputs are protected from static discharge by diode  
clamps to V and GND.  
triggered type flip-flops implemented with monolithic  
D
CC  
CMOS technology. Both are true and complemented out-  
puts from each flip-flop are externally available. All four flip-  
flops are controlled by a common clock and a common  
clear. Information at the D inputs meeting the set-up time  
requirements is transferred to the Q outputs on the positive-  
going edge of the clock pulse. The clearing operation, en-  
abled by a negative pulse at Clear input, clears all four Q  
outputs to logical ‘‘0’’ and Q’s to logical ‘‘1’’.  
Features  
Y
Wide supply voltage range  
Guaranteed noise margin  
High noise immunity  
3V to 15V  
1.0V  
Y
Y
Y
0.45 V  
CC  
(typ.)  
Low power TTL compatibility  
Fan out of 2  
driving 74L  
Connection Diagram & Truth Table  
Dual-In-Line Package  
TL/F/5900–1  
Top View  
Order Number MM54C175 or MM74C175  
Each Flip-Flop  
Inputs  
Clock  
Outputs  
Clear  
D
Q
Q
L
H
H
H
H
X
u
u
H
X
H
L
X
X
L
H
L
NC  
NC  
H
L
H
NC  
NC  
L
e
e
e
H
L
High level  
Low level  
Irrelevant  
X
e
e
Transition from low to high level  
No change  
u
NC  
C
1995 National Semiconductor Corporation  
TL/F/5900  
RRD-B30M105/Printed in U. S. A.  

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