Datasheet > TTMM54C30W/883

TTMM54C30W/883

更新时间： 2024-09-29 06:27:19

品牌	Logo	应用领域
美国国家半导体 - NSC		栅
页数	文件大小	规格书
5页	15K
描述
NAND Gate, CMOS, CDFP14

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中文翻译

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数据手册

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TTMM54C30W/883 数据手册

MICROCIRCUIT DATA SHEET

Original Creation Date: 10/19/95

Last Update Date: 05/19/97

MNMM54C30-X REV 1A0

Last Major Revision Date: 04/02/97

8-INPUT NAND GATE

General Description

The logical gate employs complementary MOS (CMOS) to achieve wide power supply operating

range, low power consumption and high noise immunity. Function and pin out compatibility

with series 54 devices minimizes design time for those designers familiar with the

standard 54 logic family.

All inputs are protected from damage due to static discharge by diode clamps to Vcc and

Gnd.

Industry Part Number

NS Part Numbers

MM54C30

MM54C30J/883

MM54C30W/883

Prime Die

MM54C30

Processing

Subgrp Description

Temp (^oC)

MIL-STD-883, Method 5004

Static tests at

+25

Static tests at

+125

-55

Static tests at

Dynamic tests at

Functional tests at

Switching tests at

+25

Quality Conformance Inspection

+125

-55

MIL-STD-883, Method 5005

+25

+125

-55

+25

+125

-55

12 3 4 5

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与TTMM54C30W/883相关器件

型号	品牌	获取价格	描述	数据表
TTMM54C30W/883B	NSC	获取价格	NAND Gate, CMOS, CDFP14
TTMM54C32F	NSC	获取价格	OR Gate, CMOS, CDFP14
TTMM54C32J/883C	NSC	获取价格	OR Gate, CMOS, CDIP14
TTMM54C32W/883B	NSC	获取价格	OR Gate, CMOS, CDFP14
TTMM54C32W/883C	NSC	获取价格	OR Gate, CMOS, CDFP14
TTMM54C73F	NSC	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, CDFP14
TTMM54C73J	NSC	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, CDIP14
TTMM54C73J/883	NSC	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, CDIP14
TTMM54C74F	TI	获取价格	D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, CDFP14
TTMM54C74J/883C	TI	获取价格	D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, CDIP14