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TSPC603PMAU6LE

更新时间: 2024-11-29 09:45:43
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
38页 599K
描述
RISC Microprocessor, 32-Bit, 166MHz, CMOS, CQFP240, CERQUAD-240

TSPC603PMAU6LE 数据手册

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TSPC603P  
PowerPC 603e RISC MICROPROCESSOR Family  
PID7v-603e Specification  
DESCRIPTION  
The PID7v-603e implementation of PowerPC603e (after  
named 603p) is a low-power implementation of reduced  
instruction set computer (RISC) microprocessors PowerPC  
family. The 603p implements 32-bit effective addresses, inte-  
gerdatatypesof8, 16and32bits, andfloating-pointdatatypes  
of 32 and 64 bits.  
CERQUAD 240  
The 603p is a low-power 2.5/3.3-volt design and provides four  
software controllable power-saving modes.  
The 603p is a superscalar processor capable of issuing and  
retiring as many as three instructions per clock. Instructions  
can execute out of order for increased performance ; however,  
the 603p makes completion appear sequential. The 603p inte-  
grates five execution units and is able to execute five instruc-  
tions in parallel.  
A suffix  
CERQUAD 240  
Ceramic Leaded Chip Carrier  
The 603p provides independent on-chip, 16-Kbyte, four-way  
set-associative, physically addressed caches for instructions  
and data and on-chip instruction and data memory manage-  
ment units (MMUs). The MMUs contain 64-entry, two-way set-  
associative, data and instruction translation lookaside buffers  
that provide support for demand-paged virtual memory  
address translation and variable-sized block translation.  
The 603p has a selectable 32 or 64-bit data bus and a 32-bit  
address bus. The 603p interface protocol allows multiple mas-  
ters to complete for system resources through a central exter-  
nal arbiter. The 603p supports single-beat and burst data  
transfers for memory accesses, and supports memory-  
mapped I/O.  
G suffix  
CBGA 255  
Ceramic Ball Grid Array  
The 603p uses an advanced, 2.5/3.3-V CMOS process tech-  
nology and maintains full interface compatibility with TTL devi-  
ces.  
The 603p integrates in system testability and debugging fea-  
tures through JTAG boundary-scan capability.  
MAIN FEATURES  
H 4.0 SPECint95, 5.3 SPECfp95 @ 166 MHz (estimated)  
H Superscalar (3 instructions per clock peak).  
H Dual 16KB caches.  
SCREENING / QUALITY / PACKAGING  
H Selectable bus clock.  
This product is manufactured in full compliance with :  
H 32-bit compatibility PowerPC implementation.  
H On chip debug support.  
H MIL-STD-883 class Q or According to TCS standards  
(planned)  
H PD typical = 3.0 Watts (166 MHz), full operating conditions.  
H Nap, doze and sleep modes for power savings.  
H Branch folding.  
H Upscreenings based upon TCS standards  
H Full military temperature range (Tc = -55°C, Tc= +125°C)  
Industrial temperature range (Tc = 40°C, Tc= +110°C)  
H 64-bit data bus (32-bit data bus option).  
H 4-Gbyte direct addressing range.  
H Internal // I/O Power Supply = 2.5 ± 5 % // 3.3 V ± 5 %.  
H 240 pin Cerquad or 255 pin CBGA packages  
H Pipelined single/double precision float unit.  
IEEE 754 compatible FPU.  
H IEEE P 1149-1 test mode (JTAG/C0P).  
H fint max = 200 MHz.  
H fbus max = 66.67 MHz.  
H Compatible CMOS input / TTL Output.  
December 1998  
1/38  

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