Datasheet > TSPC603PMGB/C8ME

TSPC603PMGB/C8ME

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
38页	704K
描述
RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255, CBGA-255

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TSPC603PMGB/C8ME 数据手册

TSPC603p

PowerPC 603e RISC MICROPROCESSOR Family

PID7v-603e Specification

DESCRIPTION

The PID7v-603e implementation of PowerPC603e (after

named 603p) is a low-power implementation of reduced

instruction set computer (RISC) microprocessors PowerPC

family. The 603p implements 32-bit effective addresses, inte-

gerdatatypesof8, 16and32bits, andfloating-pointdatatypes

of 32 and 64 bits.

CERQUAD 240

The 603p is a low-power 2.5/3.3-volt design and provides four

software controllable power-saving modes.

The 603p is a superscalar processor capable of issuing and

retiring as many as three instructions per clock. Instructions

can execute out of order for increased performance ; however,

the 603p makes completion appear sequential. The 603p inte-

grates five execution units and is able to execute five instruc-

tions in parallel.

A suffix

CERQUAD 240

Ceramic Leaded Chip Carrier

The 603p provides independent on-chip, 16-Kbyte, four-way

set-associative, physically addressed caches for instructions

and data and on-chip instruction and data memory manage-

ment units (MMUs). The MMUs contain 64-entry, two-way set-

associative, data and instruction translation lookaside buffers

that provide support for demand-paged virtual memory

address translation and variable-sized block translation.

The 603p has a selectable 32 or 64-bit data bus and a 32-bit

address bus. The 603p interface protocol allows multiple mas-

ters to complete for system resources through a central exter-

nal arbiter. The 603p supports single-beat and burst data

transfers for memory accesses, and supports memory-

mapped I/O.

The 603p uses an advanced, 2.5/3.3-V CMOS process tech-

nology and maintains full interface compatibility with TTL devi-

ces.

The 603p integrates in system testability and debugging fea-

tures through JTAG boundary-scan capability.

MAIN FEATURES

G suffix

CBGA 255

Ceramic Ball Grid Array

(To be introduced)

H 4.0 SPECint95, 5.3 SPECfp95 @ 166 MHz (estimated)

H Superscalar (3 instructions per clock peak).

H Dual 16KB caches.

H Selectable bus clock.

H 32-bit compatibility PowerPC implementation.

H On chip debug support.

H P_Dtypical = 3.0 Watts (166 MHz), full operating conditions.

H Nap, doze and sleep modes for power savings.

H Branch folding.

SCREENING / QUALITY / PACKAGING

H 64-bit data bus (32-bit data bus option).

This product is manufactured in full compliance with :

H 4-Gbyte direct addressing range.

H MIL-STD-883 class B or According to TCS standards

H Pipelined single/double precision float unit.

(planned)

IEEE 754 compatible FPU.

H Upscreenings based upon TCS standards

H IEEE P 1149-1 test mode (JTAG/C0P).

H f_intmax = 166 MHz. (200 MHz planned).

H f_busmax = 66.67 MHz.

H Full military temperature range (T_c= -55°C, Tc= +125°C)

Industrial temperature range (T_c= –40°C, T_c= +110°C)

H Internal // I/O Power Supply = 2.5 ± 5 % // 3.3 V ± 5 %.

H 240 pin Cerquad or 255 pin CBGA packages

H Compatible CMOS input / TTL Output.

June 1998

1/38

12 3 4 5 6 7...38

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与TSPC603PMGB/C8ME相关器件

型号	品牌	描述	获取价格	数据表
TSPC603PMGB/Q8LE	ATMEL	RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255, 21 MM, 3.16 MM HEIGHT, 1.27 MM PITCH,	获取价格
TSPC603PMGB/T6ME	ATMEL	RISC Microprocessor, 32-Bit, 166MHz, CMOS, CBGA255, 21 MM, 3.16 MM HEIGHT, 1.27 MM PITCH,	获取价格
TSPC603PMGB/T8LE	ATMEL	RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255, 21 MM, 3.16 MM HEIGHT, 1.27 MM PITCH,	获取价格
TSPC603PMGB/T8ME	ATMEL	RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255, 21 MM, 3.16 MM HEIGHT, 1.27 MM PITCH,	获取价格
TSPC603PMGU/T6LE	ATMEL	RISC Microprocessor, 32-Bit, 166MHz, CMOS, CBGA240, CERAMIC, BGA-240	获取价格
TSPC603PVA6LE	ATMEL	RISC Microprocessor, 32-Bit, 166MHz, CMOS, CQFP240, CERQUAD-240	获取价格

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