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TSPC603RCY8LC PDF预览

TSPC603RCY8LC

更新时间： 2024-11-28 15:55:11
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式外围集成电路
页数 文件大小 规格书
40页 670K
描述
RISC Microprocessor, 32-Bit, 200MHz, CMOS, MQFP240, CAVITY UP, METAL, QFP-240

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中文翻译

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TSPC603RCY8LC 技术参数

生命周期：Transferred零件包装代码：QFP
包装说明：FQFP,针数：240
Reach Compliance Code：unknownECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.21
Is Samacsys：N地址总线宽度：32
位大小：32边界扫描：YES
最大时钟频率：66.7 MHz外部数据总线宽度：64
格式：FLOATING POINT集成缓存：YES
JESD-30 代码：S-MQFP-G240长度：31.65 mm
低功率模式：YES端子数量：240
最高工作温度：70 °C最低工作温度：
封装主体材料：METAL封装代码：FQFP
封装形状：SQUARE封装形式：FLATPACK, FINE PITCH
认证状态：Not Qualified座面最大高度：4.1 mm
速度：200 MHz最大供电电压：2.625 V
最小供电电压：2.375 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：31.65 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR, RISC
Base Number Matches：1

TSPC603RCY8LC 数据手册

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Features  
H 5.6 SPECint95, 4.0 SPECfp95 @ 200 MHz (estimated)  
H Superscalar (3 instructions per clock peak).  
H Dual 16KB caches.  
H Selectable bus clock.  
H 32-bit compatibility PowerPC implementation.  
H On chip debug support.  
H PD typical = 2.5 Watts (200 MHz), full operating conditions.  
H Nap, doze and sleep modes for power savings.  
Description  
TSPC603r  
in CERQUAD and  
MQUAD Packages  
ThePID7t-603eimplementationofPowerPC603e(afternamed603r)isalow-powerimplementa-  
tion of reduced instruction set computer (RISC) microprocessors PowerPC family. The 603r is  
pin-to-pin compatible with PowerPC 603E and 603P in Cerquad package. The 603r implements  
32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of  
32 and 64 bits.  
The 603r is a low-power design and provides four software controllable power-saving modes.  
The 603r is a superscalar processor capable of issuing and retiring as many as three instructions  
per clock. Instructions can execute out of order for increased performance ; however, the 603r  
makes completion appear sequential. The 603r integrates five execution units and is able to exe-  
cute five instructions in parallel.  
PowerPC 603eTM RISC  
MICROPROCESSOR  
Family PID7t-603e  
Specification  
The 603r provides independent on-chip, 16-Kbyte, four-way set-associative, physically  
addressed caches for instructions and data and on-chip instruction and data memory manage-  
ment units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction  
translation lookaside buffers that provide support for demand-paged virtual memory address  
translation and variable-sized block translation.  
The 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. The603rinterfacepro-  
tocol allows multiple masters to complete for system resources through a central external arbiter.  
The 603r supports single-beat and burst data transfers for memory accesses, and supports  
memory-mapped I/O.  
TargetSpecification  
The 603r uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface  
compatibility with TTL devices.  
The 603r integrates in system testability and debugging features through JTAG boundary-scan  
capability.  
Screening / Quality /Packaging  
This product is manufactured in full  
compliance with:  
H Commercial temperature range  
(Tc = 0°C, Tc= +70°C)  
H MIL-STD-883 class Q (TBC) or  
According to TCS standards  
H Internal // I/O Power Supply  
H Full military temperature range  
(Tc = -55°C, Tc= +125°C)  
2.5 ± 5 % // 3.3 V ± 5 %  
Industrial  
temperature range  
H 240 pin Cerquad or 240 pin  
(Tc = -40°C, Tc= +110°C)  
MQUAD packages  
MQUAD 240  
CERQUAD 240  
Y suffix  
A suffix  
MQUAD 240  
Metal Quad Flat Pack  
Cavity up  
CERQUAD 240  
Ceramic Leaded Chip Carrier  
Cavity up  
August 2000  
1/40  
1234567...40

中文翻译

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