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TS87C52-MLB PDF预览

TS87C52-MLB

更新时间: 2024-09-20 20:37:43
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器时钟微控制器外围集成电路
页数 文件大小 规格书
54页 835K
描述
Microcontroller, 8-Bit, OTPROM, 40MHz, CMOS, PQCC44, PLASTIC, LCC-44

TS87C52-MLB 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:LCC包装说明:QCCJ,
针数:44Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.73具有ADC:NO
地址总线宽度:16位大小:8
最大时钟频率:40 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:8
JESD-30 代码:S-PQCC-J44JESD-609代码:e3
长度:16.55 mm湿度敏感等级:2
I/O 线路数量:32端子数量:44
PWM 通道:NO封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):245
认证状态:Not QualifiedROM可编程性:OTPROM
座面最大高度:4.57 mm速度:40 MHz
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:16.55 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

TS87C52-MLB 数据手册

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Features  
80C52 Compatible  
– 8051 Pin and Instruction Compatible  
– Four 8-bit I/O Ports  
– Three 16-bit Timer/Counters  
– 256 Bytes Scratchpad RAM  
High-speed Architecture  
40 MHz at 5V, 30 MHz at 3V  
X2 Speed Improvement Capability (6 Clocks/Machine Cycle)  
– 30 MHz at 5V, 20 MHz at 3V (Equivalent to 60 MHz at 5V, 40 MHz at 3V)  
Dual Data Pointer  
On-chip ROM/EPROM (8Kbytes)  
Programmable Clock Out and Up/Down Timer/Counter 2  
Asynchronous Port Reset  
8-bit  
Microcontroller  
8 Kbytes  
ROM/OTP,  
ROMless  
Interrupt Structure with  
– 6 Interrupt Sources  
– 4 Level Priority Interrupt System  
Full Duplex Enhanced UART  
– Framing Error Detection  
– Automatic Address Recognition  
Low EMI (Inhibit ALE)  
Power Control Modes  
– Idle Mode  
– Power-down Mode  
– Power-off Flag  
Once Mode (On-chip Emulation)  
Power Supply: 4.5 - 5.5V, 2.7 - 5.5V  
Temperature Ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)  
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 (13.9 footprint)  
TS80C32X2  
TS87C52X2  
TS80C52X2  
Description  
TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions  
of the 80C51 CMOS single chip 8-bit microcontroller.  
The TS80C52X2 retains all features of the 80C51 with extended ROM/EPROM  
capacity (8 Kbytes), 256 bytes of internal RAM, a 6-source, 4-level interrupt system,  
an on-chip oscilator and three timer/counters.  
In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel  
that facilitates multiprocessor communication (EUART) and an X2 speed improve-  
ment mechanism.  
The fully static design of the TS80C52X2 allows to reduce system power consumption  
by bringing the clock frequency down to any value, even DC, without loss of data.  
The TS80C52X2 has 2 software-selectable modes of reduced activity for further  
reduction in power consumption. In the idle mode the CPU is frozen while the timers,  
the serial port and the interrupt system are still operating. In the power-down mode the  
RAM is saved and all other functions are inoperative.  
Rev. 4184E–8051–09/02  

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