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TPS75005EVM-023 PDF预览

TPS75005EVM-023

更新时间: 2024-11-23 12:47:11
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TPS75005EVM-023

TPS75005EVM-023 数据手册

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User's Guide  
SBVU019AOctober 2011Revised October 2011  
TPS75005EVM-023  
This users guide describes the characteristics, operation, and use of the TPS75005EVM-023 evaluation  
module (EVM). The TPS75005EVM-023 is a reference design for engineering demonstration and  
evaluation of the TPS75005 dual low-dropout linear regulator (LDO) and triple voltage rail monitor from  
Texas Instruments. This users guide includes setup and configuration instructions, a complete schematic  
diagram, bill of materials (BOM), and printed circuit board (PCB) layouts for the evaluation module.  
Throughout this document, the abbreviation EVM and the term evaluation module are synonymous with  
the TPS75005EVM-023 unless otherwise noted.  
Contents  
1
2
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4
5
6
7
Introduction .................................................................................................................. 2  
Setup ......................................................................................................................... 2  
Operation ..................................................................................................................... 4  
Test Results ................................................................................................................. 5  
Thermal Guidelines and Layout Recommendations ................................................................... 6  
Board Layout ................................................................................................................ 7  
Schematic and Bill of Materials .......................................................................................... 10  
List of Figures  
1
Start-Up Sequence, SEQ Set to Logic Low .............................................................................  
Shutdown Sequence, SEQ Set to Logic Low ...........................................................................  
Load Step and Transient Response of LDO-1, VSET Set to Logic Low ............................................  
Load Step and Transient Response of LDO-2 ..........................................................................  
Third Voltage Monitor Behavior (VDET) when EXT SVS Drops Below Regulation................................  
Top Layer with Silk Screen ................................................................................................  
Top Layer ....................................................................................................................  
Internal Layer 1..............................................................................................................  
Internal Layer 2..............................................................................................................  
Bottom Layer ................................................................................................................  
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11  
TPS75005EVM-023 Schematic.......................................................................................... 10  
C2000 is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
1
SBVU019AOctober 2011Revised October 2011  
TPS75005EVM-023  
Submit Documentation Feedback  
Copyright © 2011, Texas Instruments Incorporated  

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