Datasheet > TPS51100_07

TPS51100_07

更新时间： 2024-11-01 03:58:39

品牌	Logo	应用领域
德州仪器 - TI		稳压器双倍数据速率
页数	文件大小	规格书
20页	704K
描述
3-A SINK/SOURCE DDR TERMINATION REGULATOR

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中文翻译

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数据手册

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TPS51100_07 数据手册

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SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005

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FEATURES

DESCRIPTION

Input Voltage Range: 4.75 V to 5.25 V

The TPS51100 is a 3-A sink/source tracking

VLDOIN Voltage Range: 1.2 V to 3.6 V

termination regulator. It is specifically designed for

low-cost/low-external component count systems,

where space is a premium.

3-A Sink/Source Termination Regulator

Includes Droop Compensation

Requires Only 20-µF Ceramic Output

The TPS51100 maintains fast transient response

only requiring 20-µF (2 × 10µF) of ceramic output

capacitance. The TPS51100 supports remote

sensing functions and all features required to

power the DDR and DDR2 VTT bus termination

according to the JEDEC specification. In addition,

the TPS51100 includes integrated sleep-state

controls placing VTT in High-Z in S3 (suspend to

RAM) and soft-off for VTT and VTTREF in S5

(suspend to disk). The TPS51100 is available in

the thermally efficient 10-pin MSOP PowerPAD

and is specified from −40°C to 85°C.

Capacitance

Supports High-Z in S3 and Soft-Off in S5

1.2-V Input (VLDOIN) Helps Reduce Total

Power Dissipation

Integrated Divider Tracks !/2VDDQSNS for

VTT and VTTREF

Remote Sensing (VTTSNS)

20-mV Accuracy for VTT and VTTREF

10-mA Buffered Reference (VTTREF)

Built-In Soft-Start, UVLO and OCL

Thermal Shutdown

Supports JEDEC Specifications

ORDERING INFORMATION

PLASTIC MSOP POWER PAD

APPLICATIONS

(1)

(DGQ)

DDR, DDR2 Memory Termination

−40°C to 85°C

TPS51100DGQ

(1)

SSTL−2, SSTL−18 and HSTL Termination

The DGQ package is also available taped and reeled. Add

an R suffix to the device type (i.e., TPS51100DGQR). See

the application section of the data sheet for PowerPAD

drawing and layout information.

TPS51100DGQ

VDDQSNS

VLDOIN

VTT

VIN 10

5V_IN

2 y 10 µF

GND

0.1 µF

PGND

VTTSNS VTTREF

VTTREF

Cap Manuf

Part Number

C1 TDK C2012JB0J106K

C2 TDK C1608JB1H104K

UDG−04015

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中文翻译

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与TPS51100_07相关器件

型号	品牌	获取价格	描述	数据表
TPS51100DGQ	TI	获取价格	3-A SINK/ SOURCE DDR TERMINATION REGULATOR
TPS51100DGQG4	TI	获取价格	3-A SINK/SOURCE DDR TERMINATION REGULATOR
TPS51100DGQR	TI	获取价格	3-A SINK/SOURCE DDR TERMINATION REGULATOR
TPS51100DGQRG4	TI	获取价格	3-A SINK/SOURCE DDR TERMINATION REGULATOR
TPS51103	TI	获取价格	INTEGRATED LDO WITH SWITCHOVER CIRCUIT FOR NOTEBOOK COMPUTERS
TPS51103DRCR	TI	获取价格	暂无描述
TPS51103DRCRG4	TI	获取价格	Integrated LDO with Switchover Circuit for Notebook Computers 10-SON -40 to 85
TPS51103DRCT	TI	获取价格	Integrated LDO with Switchover Circuit for Notebook Computers 10-VSON -40 to 85
TPS51103DRCTG4	TI	获取价格	DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO10, GREEN, PLASTIC, QFN-10
TPS5110PW	TI	获取价格	Synchronous Buck PWM Controller with NMOS LDO Controller 24-TSSOP -40 to 85

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