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TPS51116PWPG4 PDF预览

TPS51116PWPG4

更新时间: 2024-11-02 11:06:31
品牌 Logo 应用领域
德州仪器 - TI 开关PC双倍数据速率控制器开关式稳压器开关式控制器光电二极管电源电路开关式稳压器或控制器
页数 文件大小 规格书
42页 1191K
描述
全套 DDR、DDR2、DDR3、DDR3L、LPDDR3 和 DDR4 电源解决方案同步降压控制器、3A LDO | PWP | 20 | -40 to 85

TPS51116PWPG4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:HTSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.3Samacsys Confidence:3
Samacsys Status:ReleasedSamacsys PartID:182776
Samacsys Pin Count:21Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline PackagesSamacsys Footprint Name:PWP (R-PDSO-G20)
Samacsys Released Date:2015-05-12 08:39:58Is Samacsys:N
模拟集成电路 - 其他类型:SWITCHING CONTROLLER控制模式:CURRENT-MODE
控制技术:PULSE WIDTH MODULATION最大输入电压:5.25 V
最小输入电压:4.75 V标称输入电压:5 V
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm湿度敏感等级:2
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
最大输出电流:6 A封装主体材料:PLASTIC/EPOXY
封装代码:HTSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1 mm子类别:Switching Regulator or Controllers
表面贴装:YES切换器配置:PUSH-PULL
最大切换频率:400 kHz温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

TPS51116PWPG4 数据手册

 浏览型号TPS51116PWPG4的Datasheet PDF文件第2页浏览型号TPS51116PWPG4的Datasheet PDF文件第3页浏览型号TPS51116PWPG4的Datasheet PDF文件第4页浏览型号TPS51116PWPG4的Datasheet PDF文件第5页浏览型号TPS51116PWPG4的Datasheet PDF文件第6页浏览型号TPS51116PWPG4的Datasheet PDF文件第7页 
TPS51116  
www.ti.com................................................................................................................................................................ SLUS609HMAY 2004REVISED JULY 2009  
COMPLETE DDR, DDR2 AND DDR3 MEMORY POWER SOLUTION  
SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE  
1
FEATURES  
DESCRIPTION  
2
Synchronous Buck Controller (VDDQ)  
Wide-Input Voltage Range: 3.0-V to 28-V  
The TPS51116 provides a complete power supply for  
DDR/SSTL-2, DDR2/SSTL-18, and DDR3 memory  
systems. It integrates a synchronous buck controller  
with a 3-A sink/source tracking linear regulator and  
buffered low noise reference. The TPS51116 offers  
the lowest total solution cost in systems where space  
DCAP™ Mode with 100-ns Load Step  
Response  
Current Mode Option Supports Ceramic  
Output Capacitors  
is at  
a premium. The TPS51116 synchronous  
Supports Soft-Off in S4/S5 States  
controller runs fixed 400kHz pseudo-constant  
frequency PWM with an adaptive on-time control that  
can be configured in D-CAP™ Mode for ease of use  
and fastest transient response or in current mode to  
support ceramic output capacitors. The 3-A  
sink/source LDO maintains fast transient response  
only requiring 20-µF (2 × 10 µF) of ceramic output  
capacitance. In addition, the LDO supply input is  
available externally to significantly reduce the total  
power losses. The TPS51116 supports all of the  
sleep state controls placing VTT at high-Z in S3  
(suspend to RAM) and discharging VDDQ, VTT and  
VTTREF (soft-off) in S4/S5 (suspend to disk).  
TPS51116 has all of the protection features including  
thermal shutdown and is offered in both a 20-pin  
HTSSOP PowerPAD™ package and 24-pin 4
״
 QFN.  
Current Sensing from RDS(on) or Resistor  
2.5-V (DDR), 1.8-V (DDR2), Adjustable to  
1.5-V (DDR3) or Output Range 0.75-V to  
3.0-V  
Equipped with Powergood, Overvoltage  
Protection and Undervoltage Protection  
3-A LDO (VTT), Buffered Reference (VREF)  
Capable to Sink and Source 3 A  
LDO Input Available to Optimize Power  
Losses  
Requires only 20-µF Ceramic Output  
Capacitor  
Buffered Low Noise 10-mA VREF Output  
Accuracy 20 mV for both VREF and VTT  
Supports High-Z in S3 and Soft-Off in S4/S5  
Thermal Shutdown  
APPLICATIONS  
DDR/DDR2/DDR3/LPDDR3 Memory Power  
Supplies  
SSTL-2 SSTL-18 and HSTL Termination  
M1  
Ceramic  
IRF7821  
L1  
0.1 µF  
C1  
1 µH  
VDDQ  
1.8 V  
10 A  
VTT  
0.9 V  
2 A  
24  
23  
22  
21  
20  
19  
M2  
IRF7832  
C6  
SP−CAP  
2y150 µF  
VTT VLDOIN VBST DRVH LL  
VTTGND  
DRVL  
PGND  
1
2
3
4
5
6
18  
VREF  
0.9 V  
10 mA  
VIN  
C5  
Ceramic  
VTTSNS  
CS_GND 17  
CS 16  
R1  
5.1 kΩ  
2y10 µF  
GND  
TPS51116RGE  
MODE  
V5IN 15  
5V_IN  
R3  
5.1 Ω  
VTTREF  
COMP  
V5FILT 14  
PGOOD 13  
C2  
Ceramic  
1 µF  
C7  
Ceramic  
1 µF  
R2  
100 kΩ  
C3  
Ceramic  
2y10 µF  
NC VDDQSNS VDDQSET S3 S5 NC  
7
8
9
10  
11  
12  
C4  
PGOOD  
S3  
S5  
Ceramic  
0.033 µF  
UDG−04153  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
D-CAP, PowerPAD are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2009, Texas Instruments Incorporated  

TPS51116PWPG4 替代型号

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TPS51116PWPRG4 TI

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