TN0106
TN0110
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
Order Number / Package
BVDSS
/
RDS(ON)
ID(ON)
VGS(th)
(max)
BVDGS
(max)
(min)
TO-92
Die†
60V
3.0Ω
3.0Ω
2A
2A
2.0V
2.0V
TN0106N3
TN0110N3
—
100V
TN0110ND
7
† MIL visual screening available
Features
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) transis-
tors utilize a vertical DMOS structure and Supertex’s well-proven
silicon-gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all MOS
structures, these devices are free from thermal runaway and
thermally-induced secondary breakdown.
■ Low threshold — 2.0V max.
■ High input impedance
■ Low input capacitance — 50pF typical
■ Fast switching speeds
■ Low on resistance
■ Free from secondary breakdown
■ Low input and output leakage
■ Complementary N- and P-channel devices
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, highbreakdownvoltage, highinputimpedance, lowinput
capacitance, and fast switching speeds are desired.
Applications
■ Logic level interfaces – ideal for TTL and CMOS
Package Options
■ Solid state relays
■ Battery operated systems
■ Photo voltaic drives
■ Analog switches
■ General purpose line drivers
■ Telecom switches
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
BVDSS
BVDGS
± 20V
S G D
TO-92
Operating and Storage Temperature
Soldering Temperature*
-55°C to +150°C
300°C
* Distance of 1.6 mm from case for 10 seconds.
Note: See Package Outline section for dimensions.
7-35