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TMS320LF2401A_07 PDF预览

TMS320LF2401A_07

更新时间: 2024-10-26 05:15:47
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德州仪器 - TI 控制器
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88页 1279K
描述
DSP CONTROLLERS

TMS320LF2401A_07 数据手册

 浏览型号TMS320LF2401A_07的Datasheet PDF文件第2页浏览型号TMS320LF2401A_07的Datasheet PDF文件第3页浏览型号TMS320LF2401A_07的Datasheet PDF文件第4页浏览型号TMS320LF2401A_07的Datasheet PDF文件第5页浏览型号TMS320LF2401A_07的Datasheet PDF文件第6页浏览型号TMS320LF2401A_07的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈ ꢅ ꢉꢊ ꢋ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢌ ꢄꢈ ꢅꢉꢊ  
ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ  
SPRS161K − MARCH 2001 − REVISED JULY 2007  
D
D
D
High-Performance Static CMOS Technology  
− 25-ns Instruction Cycle Time (40 MHz)  
− 40-MIPS Performance  
D
Small Foot-Print (7 mm × 7 mm) Ideally  
Suited for Space-Constrained Applications  
D
Watchdog (WD) Timer Module  
− Low-Power 3.3-V Design  
D
10-Bit Analog-to-Digital Converter (ADC)  
− 5 Multiplexed Input Channels  
− 500 ns Minimum Conversion Time  
− Selectable Twin 8-State Sequencers  
Triggered by Event Manager  
Based on TMS320C2xx DSP CPU Core  
− Code-Compatible With 240x and  
F243/F241/C242  
− Instruction Set Compatible With F240  
On-Chip Memory  
D
D
D
Serial Communications Interface (SCI)  
− Up to 8K Words x 16 Bits of Flash  
EEPROM (2 Sectors) (LF2401A)  
− 8K Words x 16 Bits of ROM (LC2401A)  
− Programmable “Code-Security” Feature  
for the On-Chip Flash/ROM  
− Up to 1K Words x 16 Bits of  
Data/Program RAM  
Phase-Locked-Loop (PLL)-Based Clock  
Generation  
Up to 13 Individually Programmable,  
Multiplexed General-Purpose Input/Output  
(GPIO) Pins  
D
D
User-Selectable Dual External Interrupts  
(XINT1 and XINT2)  
− 544 Words of Dual-Access RAM  
− Up to 512 Words of Single-Access  
RAM  
Power Management:  
− Three Power-Down Modes  
− Ability to Power Down Each Peripheral  
Independently  
D
D
Boot ROM  
− SCI Bootloader  
Event-Manager (EV) Module (EVA), Which  
Includes:  
D
D
Real-Time JTAG-Compliant Scan-Based  
Emulation, IEEE Standard 1149.1 (JTAG)  
− Two 16-Bit General-Purpose Timers  
− Seven 16-Bit Pulse-Width Modulation  
(PWM) Channels Which Enable:  
− Three-Phase Inverter Control  
− Center- or Edge-Alignment of PWM  
Channels  
− Emergency PWM Channel Shutdown  
With External PDPINTA Pin  
− Programmable Deadband (Deadtime)  
Prevents Shoot-Through Faults  
− One Capture Unit for Time-Stamping of  
External Events  
− Input Qualifier for Select Pins  
− Synchronized A-to-D Conversion  
− Designed for AC Induction, BLDC,  
Switched Reluctance, and Stepper Motor  
Control  
Development Tools Include:  
− Texas Instruments (TI) ANSI C Compiler,  
Assembler/Linker, and Code Composer  
StudioDebugger  
− Evaluation Modules  
− Scan-Based Self-Emulation (XDS510)  
− Broad Third-Party Digital Motor Control  
Support  
D
D
32-Pin VF Low-Profile Quad Flatpack  
(LQFP)  
Extended Temperature Options (A and S)  
− A: − 40°C to 85°C  
− S: − 40°C to 125°C  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Code Composer Studio and XDS510 are trademarks of Texas Instruments.  
All trademarks are the property of their respective owners.  
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family.  
ꢎꢑ ꢏ ꢍꢓ ꢌ ꢀꢔ ꢏ ꢐ ꢍ ꢊꢀꢊ ꢕꢖ ꢗ ꢘꢙ ꢚ ꢛꢜ ꢕꢘꢖ ꢕꢝ ꢞꢟ ꢙ ꢙ ꢠꢖꢜ ꢛꢝ ꢘꢗ ꢡꢟꢢ ꢣꢕꢞ ꢛꢜ ꢕꢘꢖ ꢤꢛ ꢜꢠ ꢥ  
ꢎꢙ ꢘ ꢤꢟꢞ ꢜ ꢝ ꢞ ꢘꢖ ꢗꢘ ꢙ ꢚ ꢜ ꢘ ꢝ ꢡꢠ ꢞ ꢕꢗ ꢕꢞꢛ ꢜꢕ ꢘꢖꢝ ꢡꢠ ꢙ ꢜꢦ ꢠ ꢜꢠ ꢙ ꢚꢝ ꢘꢗ ꢀꢠꢧ ꢛꢝ ꢔꢖꢝ ꢜꢙ ꢟꢚ ꢠꢖꢜ ꢝ  
ꢝ ꢜ ꢛ ꢖꢤ ꢛ ꢙꢤ ꢨ ꢛ ꢙꢙ ꢛ ꢖ ꢜꢩꢥ ꢎꢙ ꢘ ꢤꢟꢞ ꢜꢕꢘꢖ ꢡꢙ ꢘꢞ ꢠꢝ ꢝꢕ ꢖꢪ ꢤꢘꢠ ꢝ ꢖꢘꢜ ꢖꢠ ꢞꢠ ꢝꢝ ꢛꢙ ꢕꢣ ꢩ ꢕꢖꢞ ꢣꢟꢤ ꢠ  
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ  
Copyright 2007, Texas Instruments Incorporated  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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