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TMS320LC53SPZA50 PDF预览

TMS320LC53SPZA50

更新时间： 2024-10-28 20:08:47
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路装置
页数 文件大小 规格书
87页 1247K
描述
16-BIT, 50MHz, OTHER DSP, PQFP100

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中文翻译

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TMS320LC53SPZA50 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：not_compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.92
Is Samacsys：N其他特性：3K WORDS DATA/PROG RAM
地址总线宽度：16桶式移位器：YES
位大小：16边界扫描：YES
最大时钟频率：50 MHz外部数据总线宽度：16
格式：FIXED POINT集成缓存：NO
内部总线架构：MULTIPLEJESD-30 代码：S-PQFP-G100
长度：14 mm低功率模式：YES
DMA 通道数量：外部中断装置数量：5
串行 I/O 数：端子数量：100
计时器数量：1片上数据RAM宽度：16
片上程序ROM宽度：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP100,.63SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not QualifiedRAM（字数）：1056
ROM可编程性：MROM座面最大高度：1.6 mm
子类别：Digital Signal Processors最大供电电压：3.47 V
最小供电电压：3.13 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

TMS320LC53SPZA50 数据手册

 浏览型号TMS320LC53SPZA50的Datasheet PDF文件第2页浏览型号TMS320LC53SPZA50的Datasheet PDF文件第3页浏览型号TMS320LC53SPZA50的Datasheet PDF文件第4页浏览型号TMS320LC53SPZA50的Datasheet PDF文件第5页浏览型号TMS320LC53SPZA50的Datasheet PDF文件第6页浏览型号TMS320LC53SPZA50的Datasheet PDF文件第7页 
TMS320C5x, TMS320LC5x  
DIGITAL SIGNAL PROCESSORS  
SPRS030A – APRIL 1995 – REVISED APRIL 1996  
Powerful 16-Bit TMS320C5x CPU  
Multiple Phase-Locked Loop (PLL)  
Clocking Options (×1, ×2, ×3, ×4, ×5, ×9  
Depending on Device)  
20-, 25-, 35-, and 50-ns Single-Cycle  
Instruction Execution Time for 5-V  
Operation  
Block Moves for Data/Program  
Management  
25-, 40-, and 50-ns Single-Cycle Instruction  
Execution Time for 3-V Operation  
On-Chip Scan-Based Emulation Logic  
Boundary Scan  
Single-Cycle 16 × 16-Bit Multiply/Add  
224K × 16-Bit Maximum Addressable  
External Memory Space (64K Program, 64K  
Data, 64K I/O, and 32K Global)  
Five Packaging Options  
– 100-Pin Quad Flat Package (PJ Suffix)  
– 100-Pin Thin Quad Flat Package  
(PZ Suffix)  
– 128-Pin Thin Quad Flat Package  
(PBK Suffix)  
– 132-Pin Quad Flat Package (PQ Suffix)  
– 144-Pin Thin Quad Flat Package  
(PGE Suffix)  
2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access  
On-Chip Program ROM  
1K, 3K, 6K, 9K × 16-Bit Single-Access  
On-Chip Program/Data RAM (SARAM)  
1K Dual-Access On-Chip Program/Data  
RAM (DARAM)  
Low Power Dissipation and Power-Down  
Modes:  
– 47 mA (2.35 mA/MIP) at 5 V, 40-MHz  
Clock (Average)  
Full-Duplex Synchronous Serial Port for  
Coder/Decoder Interface  
Time-Division-Multiplexed (TDM) Serial Port  
– 23 mA (1.15 mA/MIP) at 3 V, 40-MHz  
Clock (Average)  
– 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode)  
– 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode)  
– 5 µA at 5 V, Clocks Off (IDLE2 Mode)  
Hardware or Software Wait-State  
Generation Capability  
On-Chip Timer for Control Operations  
Repeat Instructions for Efficient Use of  
Program Space  
High-Performance Static CMOS Technology  
Buffered Serial Port  
Host Port Interface  
†
IEEE Standard 1149.1 Test-Access Port  
(JTAG)  
description  
The TMS320C5x generation of the Texas Instruments (TI ) TMS320 digital signal processors (DSPs) is  
fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an  
earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals,  
on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of  
‡
the ’C5x devices. They execute up to 50 million instructions per second (MIPS).  
The ’C5x devices offer these advantages:  
Enhanced TMS320 architectural design for increased performance and versatility  
Modular architectural design for fast development of spin-off devices  
Advanced integrated-circuit processing technology for increased performance  
Upward-compatible source code (source code for ’C1x and ’C2x DSPs is upward compatible with ’C5x DSPs.)  
Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation  
New static-design techniques for minimizing power consumption and maximizing radiation tolerance  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TI is a trademark of Texas Instruments Incorporated.  
†
‡
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture  
References to ’C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...87

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