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TMS320LC541PZ2-40 PDF预览

TMS320LC541PZ2-40

更新时间： 2024-10-28 19:56:43
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路装置
页数 文件大小 规格书
111页 1406K
描述
Digital Signal Processor 100-LQFP

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中文翻译

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TMS320LC541PZ2-40 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP, QFP100,.63SQ,20针数：100
Reach Compliance Code：unknown风险等级：5.81
地址总线宽度：16桶式移位器：YES
位大小：16边界扫描：YES
最大时钟频率：20 MHz外部数据总线宽度：16
格式：FIXED POINT集成缓存：NO
内部总线架构：MULTIPLEJESD-30 代码：S-PQFP-G100
长度：14 mm低功率模式：YES
DMA 通道数量：外部中断装置数量：5
串行 I/O 数：1端子数量：100
计时器数量：1片上数据RAM宽度：16
片上程序ROM宽度：16封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP100,.63SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not QualifiedRAM（字数）：2560
ROM可编程性：MROM座面最大高度：1.6 mm
子类别：Digital Signal Processors最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

TMS320LC541PZ2-40 数据手册

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TMS320C54x, TMS320LC54x, TMS320VC54x  
FIXED-POINT DIGITAL SIGNAL PROCESSORS  
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999  
D
D
D
Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
D
D
Fast Return From Interrupt  
On-Chip Peripherals  
– Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
– On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
– Full-Duplex Serial Port to Support 8- or  
16-Bit Transfers (’541, ’LC545, and  
’LC546 Only)  
– Time-Division Multiplexed (TDM) Serial  
Port (’542, ’543, ’548, and ’549 Only)  
– Buffered Serial Port (BSP) (’542, ’543,  
’LC545, ’LC546, ’548, and ’549 Only)  
– 8-Bit Parallel Host-Port Interface (HPI)  
(’542, ’LC545, ’548, and ’549)  
40-Bit Arithmetic Logic Unit (ALU)  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
D
D
D
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
– One 16-Bit Timer  
– External-Input/Output (XIO) Off Control  
to Disable the External Data Bus,  
Address Bus and Control Signals  
D
D
Data Bus With a Bus Holder Feature  
D
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
Address Bus With a Bus Holder Feature  
(’548 and ’549 Only)  
D
D
D
D
D
D
D
D
D
D
D
Extended Addressing Mode for 8M × 16-Bit  
Maximum Addressable External Program  
Space (’548 and ’549 Only)  
D
D
CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
†
IEEE Std 1149.1 (JTAG) Boundary Scan  
192K × 16-Bit Maximum Addressable  
Memory Space (64K Words Program,  
64K Words Data, and 64K Words I/O)  
Logic  
D
D
D
D
D
25-ns Single-Cycle Fixed-Point Instruction  
Execution Time [40 MIPS] for 5-V Power  
Supply (’C541 and ’C542 Only)  
On-Chip ROM with Some Configurable to  
Program/Data Memory  
20-ns and 25-ns Single-Cycle Fixed-Point  
Instruction Execution Time (50 MIPS and  
40 MIPS) for 3.3-V Power Supply (’LC54x)  
Dual-Access On-Chip RAM  
Single-Access On-Chip RAM (’548/’549)  
Single-Instruction Repeat and  
Block-Repeat Operations for Program Code  
15-ns Single-Cycle Fixed-Point Instruction  
Execution Time (66 MIPS) for 3.3-V Power  
Supply (’LC54xA, ’548, ’LC549)  
Block-Memory-Move Instructions for Better  
Program and Data Management  
12.5-ns Single-Cycle Fixed-Point  
Instruction Execution Time (80 MIPS) for  
3.3-V Power Supply (’LC548, ’LC549)  
Instructions With a 32-Bit Long Word  
Operand  
Instructions With Two- or Three-Operand  
Reads  
10-ns and 8.3-ns Single-Cycle Fixed-Point  
Instruction Execution Time (100 and 120  
MIPS) for 3.3-V Power Supply (2.5-V Core)  
(’VC549)  
Arithmetic Instructions With Parallel Store  
and Parallel Load  
Conditional Store Instructions  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...111

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TMS320LC541PZ2-40 替代型号

型号 品牌 替代类型 描述 数据表
TMS320LC546APZ-50 TI

完全替代

 FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320LC543PZ1-50 TI

类似代替

 FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320LC541BPZ-66 TI

类似代替

 FIXED-POINT DIGITAL SIGNAL PROCESSORS

与TMS320LC541PZ2-40相关器件

型号 品牌 获取价格 描述 数据表
TMS320LC541PZ2-66 TI

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 		MIXED DSP
TMS320LC541PZ2-80 TI

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 		IC MIXED DSP, Digital Signal Processor
TMS320LC541PZ-40 TI

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 		16-BIT, 100MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100
TMS320LC541PZ50 TI

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 		16-BIT, 100MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100
TMS320LC541PZ-50 TI

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 		IC 16-BIT, 100 MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100, Digital Signal Processor
TMS320LC541PZ-80 TI

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 		16-BIT, 160MHz, OTHER DSP, PQFP100, PLASTIC, TQFP-100
TMS320LC541PZL TI

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 		16-BIT, OTHER DSP, PQFP100
TMS320LC541PZS-40 TI

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 		16-BIT, 40MHz, OTHER DSP, PQFP100, PLASTIC, TQFP-100
TMS320LC542 TI

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 		FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320LC542-40 ETC

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 		Digital Signal Processor

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