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TMS320DM6437ZWT4 PDF预览

TMS320DM6437ZWT4

更新时间: 2024-01-22 09:15:41
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
305页 2529K
描述
Digital Media Processor

TMS320DM6437ZWT4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:LFBGA, BGA361,19X19,32针数:361
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01Factory Lead Time:16 weeks
风险等级:1.58其他特性:ALSO REQUIRES 3.3V SUPPLY
地址总线宽度:32桶式移位器:NO
位大小:32边界扫描:YES
最大时钟频率:27 MHz外部数据总线宽度:32
格式:FIXED POINT集成缓存:YES
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B361
JESD-609代码:e1长度:16 mm
低功率模式:YES湿度敏感等级:3
DMA 通道数量:72端子数量:361
计时器数量:5片上数据RAM宽度:8
片上程序ROM宽度:8最高工作温度:90 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA361,19X19,32
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.2,1.8,3.3 V
认证状态:Not QualifiedRAM(字数):81920
ROM可编程性:MROM座面最大高度:1.4 mm
子类别:Digital Signal Processors最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:16 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

TMS320DM6437ZWT4 数据手册

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TMS320DM6437  
Digital Media Processor  
www.ti.com  
SPRS345DNOVEMBER 2006REVISED JUNE 2008  
Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
This data manual revision history highlights the technical changes made to the SPRS345C device-specific  
data manual to make it an SPRS345D revision.  
Scope: Applicable updates to the TMS320DM643x DMP, specifically relating to the TMS320DM6437  
device, have been incorporated.  
Added 660- and 700-MHz C64x+™ device speeds.  
Added designators for low-power (-L) devices.  
SEE  
ADDITIONS/MODIFICATIONS/DELETIONS  
Global  
Updated/Changed signal name from "C_WE" to "C_WE"  
Updated/Changed signal name from "C_WEN" to "C_WE"  
Section 1.1  
Section 1.2  
Added "5280, 5600 MIPS" to "High-Performance Digital Signal Processor (DM6437)" bullet  
In first paragraph, updated/changed the following:  
First sentence from "With performance up to 4800 million instructions per second (MIPS) at a clock  
rate of 600 MHz..." to "With performance up to 5600 million instructions per second (MIPS) with a  
clock rate of 700 MHz..."  
Fifth sentence from "The DSP core can produce...for a total of 2400 million MACs per second...or a  
total of 4800 MMACS."to "The DSP core can produce...for a total of 2800 million MACs per  
second...or a total of 5600 MMACS."  
Section 2.6  
Table 2-24, Multichannel Audio Serial Port (McASP0) Terminal Functions:  
Updated/Changed AFSR0/DR0/GP[100] pin description from "... frame synchronization AFSX0..." to  
"...frame synchronization AFSR0..."  
Updated/Changed AFSX0/DX1/GP[107] pin description from "...frame synchronization AFSR0..." to  
"...frame synchronization AFSX0..."  
Table 2-21, DAC [Part of VPBE] Terminal Functions:  
Updated/Changed VDDA_1P1V description  
Section 2.8  
Section 5  
Updated/Changed Figure 2-10, Device Nomenclature, to reflect new device speeds and low-power  
designator (-L suffix).  
Added footnote to Section 5.1, Absolute Maximum Ratings Over Operating Temperature Range (Unless  
Otherwise Noted).  
Section 5  
Updated/Changed ICDD and IDDD test conditions and footnote in Section 5.3, Electrical Characteristics Over  
Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted).  
Section 6.7.1  
Table 6-15, PLLC1 Clock Frequency Ranges:  
Updated/Changed PLLOUT 1.2V-CVDD max value from "700 MHz" to "600 MHz" for  
-6/-5/-4/-L/-Q6/-Q5/-Q4 devices.  
Updated/Changed SYSCLK1 1.05V-CVDD max value from "560 MHz" to "520 MHz" for -7 devices.  
Section 5.2  
Deleted "Future variants..." footnote from table  
Section 6.7.1  
Updated/Changed sentence from "TI requires EMI filter manufacturer Murata..." to "TI recommends EMI  
filter manufacturer Murata..."  
Section 6.7.4  
Deleted "(-4, -4Q, -4S, -5, -5Q, -5S, -6)" from Table 6-19 title, Timing Requirements for MXI/CLKIN.  
Submit Documentation Feedback  
Revision History  
7

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