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TMS320DM643AGNZ6 PDF预览

TMS320DM643AGNZ6

更新时间: 2024-02-07 14:07:42
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
160页 1523K
描述
Video/Imaging Fixed-Point Digital Signal Processo

TMS320DM643AGNZ6 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-548针数:548
Reach Compliance Code:not_compliantECCN代码:3A001.A.3
HTS代码:8542.31.00.01Factory Lead Time:1 week
风险等级:5.68Is Samacsys:N
其他特性:ALSO REQUIRES 3.3V SUPPLY地址总线宽度:20
桶式移位器:NO位大小:32
边界扫描:YES最大时钟频率:133 MHz
外部数据总线宽度:64格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B548
JESD-609代码:e0长度:27 mm
低功率模式:YES湿度敏感等级:4
端子数量:548最高工作温度:90 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA548,26X26,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):220电源:1.4,3.3 V
认证状态:Not QualifiedRAM(字数):16384
座面最大高度:2.8 mm子类别:Digital Signal Processors
最大供电电压:1.44 V最小供电电压:1.36 V
标称供电电压:1.4 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:27 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

TMS320DM643AGNZ6 数据手册

 浏览型号TMS320DM643AGNZ6的Datasheet PDF文件第2页浏览型号TMS320DM643AGNZ6的Datasheet PDF文件第3页浏览型号TMS320DM643AGNZ6的Datasheet PDF文件第4页浏览型号TMS320DM643AGNZ6的Datasheet PDF文件第5页浏览型号TMS320DM643AGNZ6的Datasheet PDF文件第6页浏览型号TMS320DM643AGNZ6的Datasheet PDF文件第7页 
TMS320DM643  
Video/Imaging Fixed-Point Digital Signal Processor  
www.ti.com  
SPRS269AFEBRUARY 2005REVISED APRIL 2005  
1 TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor  
1.1 Features  
1024M-Byte Total Addressable External  
Memory Space  
High-Performance Digital Media Processor  
2-, 1.67-ns Instruction Cycle Time  
500-, 600-MHz Clock Rate  
Eight 32-Bit Instructions/Cycle  
4000, 4800 MIPS  
Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
10/100 Mb/s Ethernet MAC (EMAC)  
IEEE 802.3 Compliant  
Media Independent Interface (MII)  
8 Independent Transmit (TX) Channels and  
1 Receive (RX) Channel  
Fully Software-Compatible With C64x™  
VelociTI.2™ Extensions to VelociTI™  
Advanced Very-Long-Instruction-Word (VLIW)  
TMS320C64x™ DSP Core  
Management Data Input/Output (MDIO)  
Two Configurable Video Ports (VP1, VP2)  
Eight Highly Independent Functional Units  
With VelociTI.2™ Extensions:  
Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit  
Arithmetic per Clock Cycle  
Two Multipliers Support Four 16 x 16-Bit  
Multiplies (32-Bit Results) per Clock  
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit  
Results) per Clock Cycle  
Providing a Glueless I/F to Common Video  
Decoder and Encoder Devices  
Supports Multiple Resolutions/Video Stds  
VCXO Interpolated Control Port (VIC)  
Supports Audio/Video Synchronization  
Host-Port Interface (HPI) [32-/16-Bit]  
Load-Store Architecture With Non-Aligned  
Support  
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
Multichannel Audio Serial Port (McASP)  
Eight Serial Data Pins  
Wide Variety of I2S and Similar Bit Stream  
Format  
Integrated Digital Audio I/F Transmitter  
Supports S/PDIF, IEC60958-1, AES-3,  
CP-430 Formats  
Instruction Set Features  
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation, Bit-Counting  
VelociTI.2™ Increased Orthogonality  
Inter-Integrated Circuit (I2C Bus™)  
Multichannel Buffered Serial Port  
CLKS Input Not Supported  
Three 32-Bit General-Purpose Timers  
Sixteen General-Purpose I/O (GPIO) Pins  
Flexible PLL Clock Generator  
L1/L2 Memory Architecture  
128K-Bit (16K-Byte) L1P Program Cache  
(Direct Mapped)  
128K-Bit (16K-Byte) L1D Data Cache (2-Way  
Set-Associative)  
2M-Bit (256K-Byte) L2 Unified Mapped  
RAM/Cache (Flexible RAM/Cache  
Allocation)  
IEEE-1149.1 (JTAG) Boundary-  
Scan-Compatible  
548-Pin Ball Grid Array (BGA) Package  
(GDK and ZDK Suffixes), 0.8-mm Ball Pitch  
548-Pin Ball Grid Array (BGA) Package  
(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch  
Endianess: Little Endian, Big Endian  
64-Bit External Memory Interface (EMIF)  
0.13-µm/6-Level Cu Metal Process (CMOS)  
3.3-V I/O, 1.2-V Internal (-500)  
Glueless Interface to Asynchronous  
Memories (SRAM and EPROM) and  
Synchronous Memories (SDRAM, SBSRAM,  
ZBT SRAM, and FIFO)  
3.3-V I/O, 1.4-V Internal (-600)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
Windows is a registered trademark of Microsoft Corporation.  
I2C Bus is a trademark of Philips Electronics N.V.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2005, Texas Instruments Incorporated  

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