TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
www.ti.com
SPRS269A–FEBRUARY 2005–REVISED APRIL 2005
1 TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor
1.1 Features
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1024M-Byte Total Addressable External
Memory Space
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High-Performance Digital Media Processor
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2-, 1.67-ns Instruction Cycle Time
500-, 600-MHz Clock Rate
Eight 32-Bit Instructions/Cycle
4000, 4800 MIPS
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Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
10/100 Mb/s Ethernet MAC (EMAC)
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IEEE 802.3 Compliant
Media Independent Interface (MII)
8 Independent Transmit (TX) Channels and
1 Receive (RX) Channel
Fully Software-Compatible With C64x™
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VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x™ DSP Core
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Management Data Input/Output (MDIO)
Two Configurable Video Ports (VP1, VP2)
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Eight Highly Independent Functional Units
With VelociTI.2™ Extensions:
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Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
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Providing a Glueless I/F to Common Video
Decoder and Encoder Devices
Supports Multiple Resolutions/Video Stds
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VCXO Interpolated Control Port (VIC)
Supports Audio/Video Synchronization
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Host-Port Interface (HPI) [32-/16-Bit]
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Load-Store Architecture With Non-Aligned
Support
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Multichannel Audio Serial Port (McASP)
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Eight Serial Data Pins
Wide Variety of I2S and Similar Bit Stream
Format
Integrated Digital Audio I/F Transmitter
Supports S/PDIF, IEC60958-1, AES-3,
CP-430 Formats
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Instruction Set Features
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Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
VelociTI.2™ Increased Orthogonality
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Inter-Integrated Circuit (I2C Bus™)
Multichannel Buffered Serial Port
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CLKS Input Not Supported
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Three 32-Bit General-Purpose Timers
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
L1/L2 Memory Architecture
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128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
128K-Bit (16K-Byte) L1D Data Cache (2-Way
Set-Associative)
2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache (Flexible RAM/Cache
Allocation)
IEEE-1149.1 (JTAG) Boundary-
Scan-Compatible
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548-Pin Ball Grid Array (BGA) Package
(GDK and ZDK Suffixes), 0.8-mm Ball Pitch
548-Pin Ball Grid Array (BGA) Package
(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
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Endianess: Little Endian, Big Endian
64-Bit External Memory Interface (EMIF)
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0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/O, 1.2-V Internal (-500)
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Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM, SBSRAM,
ZBT SRAM, and FIFO)
3.3-V I/O, 1.4-V Internal (-600)
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Instruments semiconductor products and disclaimers thereto appears at the end of this document.
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I2C Bus is a trademark of Philips Electronics N.V.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2005, Texas Instruments Incorporated