TMS320DM6441
Digital Media System-on-Chip
www.ti.com
SPRS359D–SEPTEMBER 2006–REVISED MARCH 2008
1 Digital Media System-on-Chip (DMSoC)
1.1 Features
(Flexible RAM/Cache Allocation)
ARM926EJ-S Core
•
High-Performance Digital Media SoC
•
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C64x+™ DSP Clock Rate
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Support for 32-Bit and 16-Bit (Thumb Mode)
Instruction Sets
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405-MHz (Max) at 1.05 V or 513-MHz
(Max) at 1.2 V
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DSP Instruction Extensions and Single
Cycle MAC
ARM Jazelle Technology
Embedded ICE-RT™ Logic for Real-Time
Debug
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ARM926EJ-S™ Clock Rate
•
202.5-MHz (Max) at 1.05 V or 256-MHz
(Max) at 1.2 V
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Eight 32-Bit C64x+ Instructions/Cycle
4752 C64x+ MIPS
Fully Software-Compatible With C64x /
ARM9™
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ARM9 Memory Architecture
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16K-Byte Instruction Cache
8K-Byte Data Cache
16K-Byte RAM
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Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
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8K-Byte ROM
Eight Highly Independent Functional Units
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Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
Embedded Trace Buffer™ (ETB11™) With 4KB
Memory for ARM9 Debug
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Endianness: Little Endian for ARM and DSP
Video Processing Subsystem
–
•
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
Front End Provides:
•
•
CCD and CMOS Imager Interface
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
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Load-Store Architecture With Non-Aligned
Support
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Preview Engine for Real-Time Image
Processing
Glueless Interface to Common Video
Decoders
Histogram Module
Auto-Exposure, Auto-White Balance,
and Auto-Focus Module
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64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Additional C64x+™ Enhancements
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Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
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Resize Engine
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Hardware Support for Modulo Loop
Operation
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Resize Images From 1/4x to 4x
Separate Horizontal/Vertical Control
•
C64x+ Instruction Set Features
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Video Processing Subsystem (Continued)
Back End Provides:
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Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
Compact 16-Bit Instructions
Additional Instructions to Support Complex
Multiplies
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Hardware On-Screen Display (OSD)
Four 54-MHz DACs for a Combination of
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Composite NTSC/PAL Video
Luma/Chroma Separate Video
(S-video)
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Component (YPbPr or RGB) Video
(Progressive)
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C64x+ L1/L2 Memory Architecture
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32K-Byte L1P Program RAM/Cache (Direct
Mapped)
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Digital Output
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8-/16-bit YUV or up to 24-Bit RGB
HD Resolution
Up to Two Video Windows
80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
64K-Byte L2 Unified Mapped RAM/Cache
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
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