TMS320DM6443
Digital Media System-on-Chip
www.ti.com
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
1 Digital Media System-on-Chip (DMSoC)
1.1 Features
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High-Performance Digital Media SoC
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ARM926EJ-S Core
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594-MHz C64x+™ Clock Rate
297-MHz ARM926EJ-S™ Clock Rate
Eight 32-Bit C64x+ Instructions/Cycle
4752 C64x+ MIPS
Fully Software-Compatible With C64x /
ARM9™
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Support for 32-Bit and 16-Bit (Thumb®
Mode) Instruction Sets
DSP Instruction Extensions and Single
Cycle MAC
ARM® Jazelle® Technology
EmbeddedICE-RT™ Logic for Real-Time
Debug
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Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
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ARM9 Memory Architecture
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16K-Byte Instruction Cache
8K-Byte Data Cache
16K-Byte RAM
Eight Highly Independent Functional Units
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Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
8K-Byte ROM
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Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
Emulation Trace Buffer™ (ETB11™) With 4-KB
Memory for ARM9 Debug
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Endianness: Little Endian for ARM and DSP
Video Processing Subsystem
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Load-Store Architecture With Non-Aligned
Support
Resize Engine Provides:
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Resize Images From 1/4x to 4x
Separate Horizontal and Vertical Control
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64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
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Back End Provides:
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Hardware On-Screen Display (OSD)
4 - 54 MHz DACs for a Combination of
Additional C64x+™ Enhancements
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Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
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Composite NTSC/PAL Video
Luma/Chroma Separate Video
(S-video)
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Hardware Support for Modulo Loop
Operation
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Component (YPbPr or RGB) Video
(Progressive)
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C64x+ Instruction Set Features
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Digital Output
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Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
Compact 16-Bit Instructions
Additional Instructions to Support Complex
Multiplies
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8-/16-Bit YUV or up to 24-Bit RGB
HD Resolution
Up to 2 Video Windows
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External Memory Interfaces (EMIFs)
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32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
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Asynchronous16-Bit Wide EMIF (EMIFA)
With 128M-Byte Address Reach
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C64x+ L1/L2 Memory Architecture
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32K-Byte L1P Program RAM/Cache (Direct
Mapped)
80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
64K-Byte L2 Unified Mapped RAM/Cache
(Flexible RAM/Cache Allocation)
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Flash Memory Interfaces
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NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
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Flash Card Interfaces
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Multimedia Card (MMC)/Secure Digital (SD)
with Secure Data I/O (SDIO)
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Compact Flash Controller With True IDE
Mode
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