TMS320DM6467
Digital Media System-on-Chip
www.ti.com
SPRS403F–DECEMBER 2007–REVISED OCTOBER 2009
1 Digital Media System-on-Chip (DMSoC)
1.1 Features
(Flexible RAM/Cache Allocation)
ARM926EJ-S Core
•
High-Performance Digital Media SoC
•
–
–
–
–
–
594-, 729-MHz C64x+™ Clock Rate
297-, 364.5-MHz ARM926EJ-S™ Clock Rate
Eight 32-Bit C64x+ Instructions/Cycle
4752, 5832 C64x+ MIPS
Fully Software-Compatible With C64x /
ARM9™
–
Support for 32-Bit and 16-Bit (Thumb®
Mode) Instruction Sets
–
DSP Instruction Extensions and Single
Cycle MAC
–
–
ARM® Jazelle® Technology
EmbeddedICE-RT™ Logic for Real-Time
Debug
–
Supports SmartReflex™ Class 0 [-594 only]
•
1.05-V and 1.2-V Adaptive Core Voltage
•
•
ARM9 Memory Architecture
–
–
Extended Temp Available [-594 only]
Industrial Temp Available [-729 only]
–
–
–
–
16K-Byte Instruction Cache
8K-Byte Data Cache
32K-Byte RAM
•
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
8K-Byte ROM
–
Eight Highly Independent Functional Units
Embedded Trace Buffer™ (ETB11™) With 4KB
Memory for ARM9 Debug
•
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
•
•
Endianness: Little Endian for ARM and DSP
•
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
Dual Programmable High-Definition Video
Image Co-Processor (HDVICP) Engines
–
Supports a Range of Encode, Decode, and
Transcode Operations
–
Load-Store Architecture With Non-Aligned
Support
•
H.264, MPEG2, VC1, MPEG4 SP/ASP
•
99-/108-MHz Video Port Interface (VPIF)
–
–
–
–
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
–
–
Two 8-Bit SD (BT.656), Single 16-Bit HD
(BT.1120), or Single Raw (8-/10-/12-Bit)
Video Capture Channels
Two 8-Bit SD (BT.656) or Single 16-Bit HD
(BT.1120) Video Display Channels
Additional C64x+™ Enhancements
•
•
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
•
•
Video Data Conversion Engine (VDCE)
–
–
Horizontal and Vertical Downscaling
Chroma Conversion (4:2:2↔4:2:0)
•
Hardware Support for Modulo Loop
Operation
Two Transport Stream Interface (TSIF)
Modules
(One Parallel/Serial and One Serial Only)
•
C64x+ Instruction Set Features
–
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
Compact 16-Bit Instructions
Additional Instructions to Support Complex
Multiplies
–
–
TSIF for MPEG Transport Stream
Simultaneous Synchronous or
Asynchronous Input/Output Streams
–
–
–
Absolute Time Stamp Detection
PID Filter With 7 PID Filter Tables
Corresponding Clock Reference Generator
(CRGEN) Modules for System Time-Clock
Recovery
•
C64x+ L1/L2 Memory Architecture
–
–
–
32K-Byte L1P Program RAM/Cache (Direct
Mapped)
32K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
128K-Byte L2 Unified Mapped RAM/Cache
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
5秒后页面跳转
塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
英特尔震撼发布：128核心256线程的至强6性能核处理器
SK海力士量产12层HBM3E，容量高达36GB
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
