Datasheet > TMS320C6211PJA120

TMS320C6211PJA120

更新时间： 2024-10-27 22:10:15

品牌	Logo	应用领域
德州仪器 - TI		数字信号处理器
页数	文件大小	规格书
87页	1251K
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FIXED-POINT DIGITAL SIGNAL PROCESSORS

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TMS320C6211PJA120 数据手册

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SPRS073L − AUGUST 1998 − REVISED JUNE 2005

Excellent Price/Performance Digital Signal

Processors (DSPs): TMS320C62x

(TMS320C6211 and TMS320C6211B)

− Eight 32-Bit Instructions/Cycle

− C6211, C6211B, C6711, and C6711B are

Pin-Compatible

− 150-, 167-MHz Clock Rates

− 6.7-, 6-ns Instruction Cycle Time

− 1200, 1333 MIPS

Device Configuration

− Boot Mode: HPI, 8-, 16-, and 32-Bit ROM

Boot

− Endianness: Little Endian, Big Endian

32-Bit External Memory Interface (EMIF)

− Glueless Interface to Asynchronous

Memories: SRAM and EPROM

− Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

− 512M-Byte Total Addressable External

Memory Space

− Extended Temperature Device (C6211B)

VelociTI Advanced Very Long Instruction

Word (VLIW) C62x DSP Core (C6211/11B)

− Eight Highly Independent Functional

Units:

Enhanced Direct-Memory-Access (EDMA)

Controller (16 Independent Channels)

16-Bit Host-Port Interface (HPI)

− Access to Entire Memory Map

− Six ALUs (32-/40-Bit)

− Two 16-Bit Multipliers (32-Bit Results)

− Load-Store Architecture With 32 32-Bit

General-Purpose Registers

− Instruction Packing Reduces Code Size

− All Instructions Conditional

Two Multichannel Buffered Serial Ports

(McBSPs)

− Direct Interface to T1/E1, MVIP, SCSA

Framers

− ST-Bus-Switching Compatible

− Up to 256 Channels Each

− AC97-Compatible

− Serial-Peripheral-Interface (SPI)

Compatible (Motorola)

Instruction Set Features

− Byte-Addressable (8-, 16-, 32-Bit Data)

− 8-Bit Overflow Protection

− Saturation

− Bit-Field Extract, Set, Clear

− Bit-Counting

Two 32-Bit General-Purpose Timers

− Normalization

Flexible Phase-Locked-Loop (PLL) Clock

Generator

L1/L2 Memory Architecture

− 32K-Bit (4K-Byte) L1P Program Cache

(Direct Mapped)

− 32K-Bit (4K-Byte) L1D Data Cache

(2-Way Set-Associative)

†

IEEE-1149.1 (JTAG )

Boundary-Scan-Compatible

256-Pin Ball Grid Array (BGA) Package

(GFN and ZFN Suffixes)

− 512K-Bit (64K-Byte) L2 Unified Mapped

RAM/Cache

0.18-µm/5-Level Metal Process

− CMOS Technology

(Flexible Data/Program Allocation)

3.3-V I/Os, 1.8-V Internal

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.

Motorola is a trademark of Motorola, Inc.

All trademarks are the property of their respective owners.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

12 3 4 5 6 7...87

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与TMS320C6211PJA120相关器件

型号	品牌	获取价格	描述	数据表
TMS320C6211PJA150	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6211PJA167	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6211PQ100	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6211PQ120	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6211PQ150	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6211PQ167	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6211PQA100	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6211PQA120	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6211PQA150	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMS320C6211PQA167	TI	获取价格	FIXED-POINT DIGITAL SIGNAL PROCESSORS

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