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SPRS196H − MARCH 2002 − REVISED JULY 2004
D
D
Low-Cost, High-Performance Fixed-Point
DSP − TMS320C6411
− 3.33-ns Instruction Cycle Time
− 300-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− Twenty-Eight Operations/Cycle
− 2400 MIPS
− Fully Software-Compatible With
TMS320C62x
VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2 Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
D
D
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Host-Port Interface (HPI)
− User-Configurable Bus Width (32-/16-Bit)
− Access to Entire Memory Map
D
32-Bit/33-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.2
− Access to Entire Memory Map
− Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
− Four-Wire Serial EEPROM Interface
− PCI Interrupt Request Under DSP
Program Control
− DSP Interrupt Via PCI I/O Cycle
D
Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial Peripheral Interface (SPI)
Compatible (Motorola)
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Non-Aligned Load-Store Architecture
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D
D
Three 32-Bit General-Purpose Timers
D
D
Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2 Increased Orthogonality
L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache (Flexible RAM/Cache
Allocation)
Sixteen General-Purpose I/O (GPIO) Pins
− Programmable Interrupt/Event
Generation Modes
D
D
D
D
D
Flexible PLL Clock Generator
†
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package
(GLZ and ZLZ Suffix), 0.8-mm Ball Pitch
0.13-µm/6-Level Copper Metal Process
− CMOS Technology
3.3-V I/Os, 1.2-V Internal
D
32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 512M-Byte Total Addressable External
Memory Space
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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Copyright 2004, Texas Instruments Incorporated
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ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
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