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TMP320C50KGDL57C PDF预览

TMP320C50KGDL57C

更新时间: 2024-09-14 20:41:23
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 外围集成电路
页数 文件大小 规格书
7页 138K
描述
Digital Signal Processor, 16-Ext Bit, CMOS, DIE-117

TMP320C50KGDL57C 技术参数

生命周期:Contact Manufacturer包装说明:DIE,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.7Base Number Matches:1

TMP320C50KGDL57C 数据手册

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TMP320C50KGD, TMP320LC50KGD  
DIGITAL SIGNAL PROCESSOR  
KNOWN GOOD DIE  
SGZS008C -- JULY 1996 -- REVISED JUNE 2000  
D
25-ns, 35-ns, and 50-ns Single-Cycle  
Instruction Execution Time for 5-V  
Operation  
D
D
D
D
D
D
D
D
16-Bit Parallel Logic Unit (PLU)  
16 × 16-Bit Multiplier, 32-Bit Product  
Eleven Context Switch Registers  
D
D
D
50-ns Single-Cycle Instruction Execution  
Time for 3.3-V Operation  
Two Buffers for Circular Addressing  
Full-Duplex Synchronous Serial Port  
Time-Division Multiplexed Serial Port (TDM)  
Timer With Control and Counter Registers  
Source-Code Compatible With All ’C1x and  
’C2x Devices  
RAM-Based Operation  
-- 9 K - W o r d × 16-Bit Single-Access On-Chip  
Program/Data RAM  
Sixteen Software-Programmable Wait-State  
Generators  
-- 1056-Word × 16-Bit Dual-Access On-Chip  
Data RAM  
D
D
D
D
Divide-By-1 Clock Option  
IEEE Standard 1149.1Test Access Port  
D
D
2K-Word × 16-Bit On-Chip Boot ROM  
Operations are Fully Static  
224K-Word × 16-Bit Maximum Addressable  
External Memory Space (64K-Word  
Program, 64K-Word Data, 64K-Word I/O,  
and 32K-Word Global)  
Fabricated Using the Texas Instruments (TI)  
Enhanced Performance Implanted CMOS  
(EPIC) 0.64-μm Technology  
D
32-Bit Arithmetic Logic Unit (ALU)  
-- 32-Bit Accumulator (ACC)  
-- 32-Bit Accumulator Buffer (ACCB)  
description  
The TMP320C50KGD digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor  
manufactured in 0.64-μm double-level metal CMOS technology. The TMP320LC50KGD has the same  
functionality as the ’C50KGD except for operation at 3.3 V instead of 5 V.  
Texas Instruments Military Products currently employs three primary processes for the development of a known  
good die (KGD), one of which is applied to the TMP320C50 and TMP320LC50 devices. This process, known  
as hot-chuck-probe, uses a standard probed product that is tested again, this time at full data sheet  
specifications, in wafer form at speed and elevated temperature (85°C). Each individual die then is sawed,  
inspected, and packed for shipment. This flow produces a bare die that has been temperature-tested at speed  
and is known to be good, without having to use a temporary package.  
A number of enhancements to the basic ’C2x architecture give the ’C5x a minimum 2x performance over the  
previous generation. A four-deep instruction pipeline, incorporating delayed branching, delayed call to  
subroutine, and delayed return from subroutine, allows the ’C5x to perform instructions in fewer cycles. The  
addition of a PLU gives the ’C5x a method of manipulating bits in data memory without using the ACC and ALU.  
The ’C5x has additional shifting and scaling capability for proper alignment of multiplicands or storage of values  
to data memory.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
IEEE Standard 1149.1--1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture  
EPIC is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
Copyright © 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443  

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