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ꢐ ꢏꢑ ꢒꢀ ꢓꢔꢉ ꢕꢂ ꢑꢓ ꢔꢀ ꢊꢓ ꢉꢓ ꢀꢒꢏ ꢍꢓ ꢉ ꢔꢒꢏ ꢂꢖ ꢑ ꢆꢗ ꢍ ꢍꢑ ꢖ
ꢈꢔꢑ ꢘ ꢔ ꢉ ꢑ ꢑ ꢊ ꢊ ꢓꢗ ꢍ
SGUS023B − APRIL 1997 − REVISED OCTOBER 2001
D
D
Commercial Operating Free-Air
Temperature Range
−0°C to 70°C
Military Operating Free-Air
Temperature Range
−55°C to 125°C, QML Processing
Fast Instruction Cycle Time of 50 ns
D
D
D
D
Two 32-Bit Timers With Control and
Counter Registers
Validated Ada Compiler
64-Word × 32-Bit Instruction Cache
On-Chip Direct Memory Access (DMA)
Controller for Concurrent I/O and CPU
Operation
D
D
D
D
D
Two 1K × 32-Bit Single-Cycle Dual-Access
On-Chip RAM Blocks
D
D
D
Flexible Boot Program Loader for the
’320C31KGDB Instead of the ROM
32-Bit Instruction and Data Words,
24-Bit Addresses
One 32-Bit External Port for the
’320C31KGDB (24-Bit Address)
Integer, Floating-Point, and Logical
Operations
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
40- or 32-Bit Floating-Point/Integer
Multiplier and Arithmetic Logic Unit (ALU)
D
D
Zero-Overhead Loops With Single-Cycle
Branches
D
24 × 24-Bit Integer Multiplier, 32-Bit Product
32 × 32-Bit Floating-Point Multiplier,
40-Bit Product
D
Interlocked Instructions for
Multiprocessing Support
D
Parallel ALU and Multiplier Execution in a
Single Cycle
D
D
D
D
Two- and Three-Operand Instructions
Conditional Calls and Returns
Block Repeat Capability
D
32-Bit Barrel Shifter
D
Eight Extended-Precision Registers
(Accumulators)
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC) Technology by
Texas Instruments
D
D
Circular and Bit-Reversed Addressing
Capabilities
One Independent Bidirectional Serial Port
With Support for 8-, 16-, 24-, or 32-Bit
Transfers
description
The TMP/SMJ320C31KGDB and SMJ320LC31KGDB digital signal processors (DSPs) known good dies
(KGDs) are high-performance, 32-bit floating-point processors manufactured in 0.72-µm, double-level metal
CMOS technology.
The TMP/SMJ320C31KGDB and SMJ320LC31KGDB internal busing and special digital signal processing
instruction set have the speed and flexibility to execute up to 40 million floating-point operations per second
(MFLOPS). The devices optimize speed by implementing functions in hardware that other processors
implement through software or microcode. This hardware-intensive approach provides performance previously
unavailable on a single chip.
The devices can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle.
Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal
dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High
performance and ease of use are results of these features.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
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Copyright 2001, Texas Instruments Incorporated
ꢑ ꢛ ꢦ ꢞ ꢝꢩ ꢤꢣ ꢡꢢ ꢣꢝ ꢟꢦ ꢨꢚ ꢠꢛ ꢡ ꢡꢝ ꢁꢓ ꢏꢕ ꢂꢖ ꢐ ꢕꢃꢰꢱ ꢃꢱꢌ ꢠꢨꢨ ꢦꢠ ꢞ ꢠ ꢟꢥ ꢡꢥꢞ ꢢ ꢠ ꢞ ꢥ ꢡꢥ ꢢꢡꢥ ꢩ
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1
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