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TMP320C40

更新时间： 2024-11-18 22:07:07
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
62页 1062K
描述
DIGITAL SIGNAL PROCESSORS

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TMP320C40 数据手册

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SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001  
†
D
D
D
D
SMJ: QML Processing to MIL–PRF–38535  
SM: Standard Processing  
TMP: Commercial Level Processing TAB  
D
D
IEEE Standard 1149.1 Test-Access Port  
(JTAG)  
Two Identical External Data and Address  
Buses Supporting Shared Memory Systems  
and High Data-Rate, Single-Cycle  
Transfers:  
– High Port-Data Rate of 100 MBytes/s  
(Each Bus)  
Operating Temperature Ranges:  
– Military (M) –55°C to 125°C  
– Special (S) –55°C to 100°C  
– Commercial (C) –25°C to 85°C  
– Commercial (L) 0°C to 70°C  
– 16G-Byte Continuous  
Program/Data/Peripheral Address Space  
– Memory-Access Request for Fast,  
Intelligent Bus Arbitration  
– Separate Address-, Data-, and  
Control-Enable Pins  
– Four Sets of Memory-Control Signals  
Support Different Speed Memories in  
Hardware  
D
Highest Performance Floating-Point Digital  
Signal Processor (DSP)  
– C40-60:  
33-ns Instruction Cycle Time:  
60 MFLOPS, 30 MIPS, 330 MOPS,  
384 MBps  
– C40-50:  
40-ns Instruction Cycle Time:  
50 MFLOPS, 25 MIPS, 275 MOPS,  
320 MBps  
D
Packaging:  
– 325-Pin Ceramic Grid Array (GF Suffix)  
– 352-Lead Ceramic Quad Flatpack  
(HFH Suffix)  
– C40-40:  
50-ns Instruction Cycle Time:  
40 MFLOPS, 20 MIPS, 220 MOPS,  
256 MBps  
– 324-Pad JEDEC-Standard TAB Frame  
D
D
Fabricated Using Enhanced Performance  
Implanted CMOS (EPIC ) Technology by  
Texas Instruments (TI )  
Separate Internal Program, Data, and DMA  
Coprocessor Buses for Support of Massive  
Concurrent Input/Output (I/O) of Program  
and Data Throughput, Maximizing  
Sustained Central Processing Unit (CPU)  
Performance  
D
D
D
D
D
D
D
Six Communications Ports  
6-Channel Direct Memory Access (DMA)  
Coprocessor  
Single-Cycle Conversion to and From  
IEEE-745 Floating-Point Format  
Ǹ
x
Single Cycle 1/x, 1/  
Source-Code Compatible With SMJ320C30  
Validated Ada Compiler  
Single-Cycle 40-Bit Floating-Point,  
32-Bit Integer Multipliers  
12 40-Bit Registers, 8 Auxiliary Registers,  
14 Control Registers, and 2 Timers  
D
On-Chip Program Cache and  
Dual-Access/Single-Cycle RAM for  
Increased Memory-Access Performance  
– 512-Byte Instruction Cache  
– 8K Bytes of Single-Cycle Dual-Access  
Program or Data RAM  
– ROM-Based Bootloader Supports  
Program Bootup Using 8-, 16-, or 32-Bit  
Memories Over Any One of the  
Communications Ports  
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture.  
EPIC and TI are trademarks of Texas Instruments Incorporated.  
Copyright 2001, Texas Instruments Incorporated  
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...62

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