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TLV5630

更新时间： 2024-09-12 22:49:43
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
15页 267K
描述
8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE

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TLV5630 数据手册

 浏览型号TLV5630的Datasheet PDF文件第2页浏览型号TLV5630的Datasheet PDF文件第3页浏览型号TLV5630的Datasheet PDF文件第4页浏览型号TLV5630的Datasheet PDF文件第5页浏览型号TLV5630的Datasheet PDF文件第6页浏览型号TLV5630的Datasheet PDF文件第7页 
TLV5630  
TLV5631  
TLV5632  
www.ti.com  
SLAS269D–MAY 2000–REVISED MARCH 2004  
8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG  
CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE  
FEATURES  
APPLICATIONS  
•
•
•
•
•
Digital Servo Control Loops  
Digital Offset and Gain Adjustment  
Industrial Process Control  
Machine and Motion Control Devices  
Mass Storage Devices  
•
Eight Voltage Output DACs in One Package  
– TLV5630 . . . 12-Bit  
– TLV5631 . . . 10-Bit  
– TLV5632 . . . 8-Bit  
– 1 µs in Fast Mode  
DW OR PW PACKAGE  
(TOP VIEW)  
– 3 µs in Slow Mode  
•
Programmable Settling Time vs Power  
Consumption  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DGND  
DIN  
SCLK  
FS  
DV  
DD  
– 1 µs in Fast Mode  
DOUT  
LDAC  
MODE  
REF  
OUTD  
OUTC  
OUTB  
OUTA  
– 3 µs in Slow Mode  
– 18 mW in Slow Mode at 3 V  
– 48 mW in Fast Mode at 3 V  
Compatible With TMS320 and SPI Serial Ports  
Monotonic Over Temperature  
Low Power Consumption:  
– 18 mW in Slow Mode at 3 V  
– 48 mW in Fast Mode at 3 V  
Power-Down Mode  
PRE  
OUTE  
OUTF  
OUTG  
OUTH  
AGND  
•
•
•
AV  
DD  
•
•
•
Internal Reference  
Data Output for Daisy-Chaining  
DESCRIPTION  
The TLV5630, TLV5631, and TLV5632 are pin-compatible, eight-channel, 12-/10-/8-bit voltage output DACs  
each with a flexible serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and  
Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits.  
Additional features are a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs,  
and a data output which can be used to cascade multiple devices, and an internal programmable band-gap  
reference.  
The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to  
allow the designer to optimize speed vs power dissipation. The buffered, high-impedance reference input can be  
connected to the supply voltage.  
Implemented with a CMOS process, the DACs are designed for single-supply operation from 2.7 V to 5.5 V. The  
devices are available in 20-pin SOIC and TSSOP packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2000–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

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