5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > 串行 IO/通信控制器> TL16C554IFNR
TL16C554IFNR PDF预览

TL16C554IFNR

更新时间： 2024-01-14 07:52:58
品牌 Logo 应用领域
德州仪器 - TI 通信
页数 文件大小 规格书
35页 589K
描述
ASYNCHRONOUS COMMUNICATIONS ELEMENT

阅读下载

中文翻译

获取价格

TL16C554IFNR 数据手册

 浏览型号TL16C554IFNR的Datasheet PDF文件第2页浏览型号TL16C554IFNR的Datasheet PDF文件第3页浏览型号TL16C554IFNR的Datasheet PDF文件第4页浏览型号TL16C554IFNR的Datasheet PDF文件第5页浏览型号TL16C554IFNR的Datasheet PDF文件第6页浏览型号TL16C554IFNR的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃꢄ ꢅꢅ ꢆꢈ  
ꢉꢊꢋ ꢌꢄꢍꢎ ꢏꢌ ꢏꢐꢊ ꢄꢏ ꢑ ꢑꢐꢌ ꢈꢄꢉꢀ ꢈꢏ ꢌꢊ ꢒ ꢁꢒ ꢑ ꢒꢌ ꢀ  
ꢓ
ꢓ
SLLS165G − JANUARY 1994 − REVISED MARCH 2006  
D
D
D
Integrated Asynchronous Communications  
Element  
D
Fully Programmable Serial Interface  
Characteristics:  
− 5-, 6-, 7-, or 8-Bit Characters  
− Even-, Odd-, or No-Parity Bit  
− 1-, 1 1/2-, or 2-Stop Bit Generation  
− Baud Generation (DC to 1-Mbit Per  
Second)  
Consists of Four Improved TL16C550 ACEs  
Plus Steering Logic  
In FIFO Mode, Each ACE Transmitter and  
Receiver Is Buffered With 16-Byte FIFO to  
Reduce the Number of Interrupts to CPU  
D
D
D
D
False Start Bit Detection  
D
In TL16C450 Mode, Hold and Shift  
Registers Eliminate Need for Precise  
Synchronization Between the CPU and  
Serial Data  
Complete Status Reporting Capabilities  
Line Break Generation and Detection  
Internal Diagnostic Capabilities:  
− Loopback Controls for Communications  
Link Fault Isolation  
− Break, Parity, Overrun, Framing Error  
Simulation  
D
D
Up to 16-MHz Clock Rate for up to 1-Mbaud  
Operation  
Programmable Baud Rate Generators  
Which Allow Division of Any Input  
16  
Reference Clock by 1 to (2 ꢀ −ꢀ 1) and  
D
D
D
Fully Prioritized Interrupt System Controls  
Generate an Internal 16 × Clock  
Modem Control Functions (CTS, RTS, DSR,  
DTR, RI, and DCD)  
D
D
Adds or Deletes Standard Asynchronous  
Communication Bits (Start, Stop, and  
Parity) to or From the Serial Data Stream  
3-State Outputs Provide TTL Drive  
Capabilities for Bidirectional Data Bus and  
Control Bus  
Independently Controlled Transmit,  
Receive, Line Status, and Data Set  
Interrupts  
description  
The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous  
communications element (ACE). Each channel performs serial-to-parallel conversion on data characters  
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted  
by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional  
operation by the CPU. The information obtained includes the type and condition of the operation performed and  
any error conditions encountered.  
The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates  
the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in  
both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on  
the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes  
a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and  
16  
(2 −1).  
The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and  
in an 80-pin (TQFP) PN package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢔ
ꢔ
ꢎ
ꢏ
ꢥ
ꢕ
ꢠ
ꢐ
ꢄ
ꢞ
ꢀ
ꢟ
ꢈ
ꢙ
ꢏ
ꢗ
ꢌ
ꢘ
ꢕ
ꢉ
ꢀ
ꢉ
ꢖ
ꢗ
ꢡ
ꢘ
ꢙ
ꢟ
ꢚ
ꢛ
ꢜ
ꢜ
ꢝ
ꢝ
ꢖ
ꢖ
ꢙ
ꢙ
ꢗ
ꢗ
ꢖ
ꢞ
ꢞ
ꢢ
ꢟ
ꢠ
ꢚ
ꢚ
ꢡ
ꢡ
ꢗ
ꢝ
ꢜ
ꢛ
ꢞ
ꢞ
ꢙ
ꢘ
ꢢ
ꢀꢡ  
ꢠ
ꢣ
ꢞ
ꢤ
ꢖ
ꢟ
ꢜ
ꢞ
ꢝ
ꢖ
ꢝ
ꢙ
ꢚ
ꢗ
ꢠ
ꢥ
ꢜ
ꢗ
ꢝ
ꢝ
ꢡ
ꢞ
ꢦ
Copyright 1994 − 2006, Texas Instruments Incorporated  
ꢚ
ꢙ
ꢟ
ꢝ
ꢙ
ꢚ
ꢛ
ꢝ
ꢙ
ꢞ
ꢢ
ꢖ
ꢘ
ꢖ
ꢟ
ꢡ
ꢚ
ꢝ
ꢧ
ꢝ
ꢡ
ꢚ
ꢙ
ꢘ
ꢨ
ꢜ
ꢈ
ꢗ
ꢛ
ꢡ
ꢞ
ꢝ
ꢜ
ꢗ
ꢥ
ꢜ
ꢚ
ꢥ
ꢩ
ꢜ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
ꢚ
ꢚ
ꢜ
ꢗ
ꢝ
ꢪ
ꢦ
ꢔ
ꢚ
ꢙ
ꢥ
ꢠ
ꢟ
ꢝ
ꢖ
ꢙ
ꢗ
ꢢ
ꢚ
ꢙ
ꢟ
ꢡ
ꢞ
ꢞ
ꢖ
ꢗ
ꢫ
ꢥ
ꢙ
ꢡ
ꢞ
ꢗ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢪ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢥ
ꢡ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...35

中文翻译

下载PDF

TL16C554IFNR 替代型号

型号 品牌 替代类型 描述 数据表
TL16C554IFN TI

完全替代

 ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C554FN TI

类似代替

 ASYNCHRONOUS COMMUNICATIONS ELEMENT

与TL16C554IFNR相关器件

型号 品牌 获取价格 描述 数据表
TL16C554IFNRG4 TI

获取价格

 		ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C554IPN TI

获取价格

 		ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C554IPNG4 TI

获取价格

 		ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C554IPNRG4 TI

获取价格

 		IC 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP80, GREEN, TQFP-80, Serial IO/Communi
TL16C554PN TI

获取价格

 		ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C554PNG4 TI

获取价格

 		ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C554PNR TI

获取价格

 		ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C554PNRG4 TI

获取价格

 		ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C750 TI

获取价格

 		ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
TL16C750CFN TI

获取价格

 		1 CHANNEL(S), 1Mbps, SERIAL COMM CONTROLLER, PQCC44

与TL16C554IFNR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证