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TL16C554IFN PDF预览

TL16C554IFN

更新时间： 2024-09-29 22:16:07
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输PC时钟
页数 文件大小 规格书
33页 477K
描述
ASYNCHRONOUS COMMUNICATIONS ELEMENT

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TL16C554IFN 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：LCC
包装说明：QCCJ, LDCC68,1.0SQ针数：68
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01Factory Lead Time：1 week
风险等级：1.5Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：182354
Samacsys Pin Count：68Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Plastic Leaded Chip CarrierSamacsys Footprint Name：FN (S-PQCC-J68)
Samacsys Released Date：2015-04-13 16:56:59Is Samacsys：N
地址总线宽度：3边界扫描：NO
最大时钟频率：16 MHz通信协议：ASYNC, BIT
数据编码/解码方法：NRZ最大数据传输速率：0.125 MBps
外部数据总线宽度：8JESD-30 代码：S-PQCC-J68
JESD-609代码：e4长度：24.23 mm
低功率模式：NO湿度敏感等级：3
DMA 通道数量：I/O 线路数量：
串行 I/O 数：4端子数量：68
片上数据RAM宽度：最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC68,1.0SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not QualifiedRAM（字数）：0
座面最大高度：4.57 mm子类别：Serial IO/Communication Controllers
最大压摆率：50 mA最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：24.23 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：1

TL16C554IFN 数据手册

 浏览型号TL16C554IFN的Datasheet PDF文件第2页浏览型号TL16C554IFN的Datasheet PDF文件第3页浏览型号TL16C554IFN的Datasheet PDF文件第4页浏览型号TL16C554IFN的Datasheet PDF文件第5页浏览型号TL16C554IFN的Datasheet PDF文件第6页浏览型号TL16C554IFN的Datasheet PDF文件第7页 
TL16C554, TL16C554I  
ASYNCHRONOUS COMMUNICATIONS ELEMENT  
SLLS165D – JANUARY 1994 – REVISED JULY 1998  
Integrated Asynchronous Communications  
Element  
Fully Programmable Serial Interface  
Characteristics:  
– 5-, 6-, 7-, or 8-Bit Characters  
– Even-, Odd-, or No-Parity Bit  
– 1-, 1 1/2-, or 2-Stop Bit Generation  
– Baud Generation (DC to 1-Mbit Per  
Second)  
Consists of Four Improved TL16C550 ACEs  
Plus Steering Logic  
In FIFO Mode, Each ACE Transmitter and  
Receiver Is Buffered With 16-Byte FIFO to  
Reduce the Number of Interrupts to CPU  
False Start Bit Detection  
In TL16C450 Mode, Hold and Shift  
Registers Eliminate Need for Precise  
Synchronization Between the CPU and  
Serial Data  
Complete Status Reporting Capabilities  
Line Break Generation and Detection  
Internal Diagnostic Capabilities:  
– Loopback Controls for Communications  
Link Fault Isolation  
Up to 16-MHz Clock Rate for up to 1-Mbaud  
Operation  
– Break, Parity, Overrun, Framing Error  
Simulation  
Programmable Baud Rate Generators  
Which Allow Division of Any Input  
Reference Clock by 1 to (2 –1) and  
16  
Fully Prioritized Interrupt System Controls  
Generate an Internal 16 × Clock  
Modem Control Functions (CTS, RTS, DSR,  
DTR, RI, and DCD)  
Adds or Deletes Standard Asynchronous  
Communication Bits (Start, Stop, and  
Parity) to or From the Serial Data Stream  
3-State Outputs Provide TTL Drive  
Capabilities for Bidirectional Data Bus and  
Control Bus  
Independently Controlled Transmit,  
Receive, Line Status, and Data Set  
Interrupts  
description  
The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous  
communications element (ACE). Each channel performs serial-to-parallel conversion on data characters  
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted  
bytheCPU. ThecompletestatusofeachchannelofthequadrupleACEcanbereadatanytimeduringfunctional  
operation by the CPU. The information obtained includes the type and condition of the operation performed and  
any error conditions encountered.  
The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates  
the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in  
both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on  
the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes  
a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and  
16  
(2 –1).  
The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and  
in an 80-pin (TQFP) PN package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...33

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TL16C554IFN 替代型号

型号 品牌 替代类型 描述 数据表
TL16C554AFN TI

类似代替

 ASYNCHRONOUS-COMMUNICATIONS ELEMENT
TL16C554FN TI

类似代替

 ASYNCHRONOUS COMMUNICATIONS ELEMENT

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