Datasheet > 微控制器和处理器 > 串行 IO/通信控制器> TL16C2550PFBG4

TL16C2550PFBG4

更新时间： 2024-01-23 10:15:08

品牌	Logo	应用领域
德州仪器 - TI		微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
页数	文件大小	规格书
47页	1091K
描述
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS

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TL16C2550PFBG4 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	TQFP-48	针数：	48
Reach Compliance Code：	compliant	HTS代码：	8542.31.00.01
Factory Lead Time：	6 weeks	风险等级：	5.74
Is Samacsys：	N	其他特性：	ALSO OPERATES AT 1.8V MINIMUM SUPPLY AT 10MHZ
地址总线宽度：	3	边界扫描：	NO
最大时钟频率：	24 MHz	通信协议：	ASYNC, BIT
最大数据传输速率：	0.1875 MBps	外部数据总线宽度：	8
JESD-30 代码：	S-PQFP-G48	JESD-609代码：	e4
长度：	7 mm	低功率模式：	NO
湿度敏感等级：	2	串行 I/O 数：	2
端子数量：	48	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装等效代码：	TQFP48,.35SQ
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	1.8/5 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	Serial IO/Communication Controllers	最大压摆率：	7.5 mA
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7 mm
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	Base Number Matches：	1

TL16C2550PFBG4 数据手册

TL16C2550

www.ti.com

SLWS161D–JUNE 2005–REVISED OCTOBER 2006

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

PFB NO.

FN NO.

RHB NO.

Address 0 select bit. Internal registers address selection

Address 1 select bit. Internal registers address selection

Address 2 select bit. Internal registers address selection

Carrier detect (active low). These inputs are associated with individual

UART channels A and B. A low on these pins indicates that a carrier has

been detected by the modem for that channel. The state of these inputs is

reflected in the modem status register (MSR).

CDA, CDB

CSA, CSB

40, 16

10, 11

42, 21

16, 17

–

Chip select A and B (active low). These pins enable data transfers between

the user CPU and the TL16C2550 for the channel(s) addressed. Individual

UART sections (A, B) are addressed by providing a low on the respective

CSA and CSB pins.

7, 8

Clear to send (active low). These inputs are associated with individual

UART channels A and B. A logic low on the CTS pins indicates the modem

or data set is ready to accept transmit data from the 2550. Status can be

tested by reading MSR bit 4. These pins only affect the transmit and

receive operations when auto CTS function is enabled through the

enhanced feature register (EFR) bit 7, for hardware flow control operation.

CTSA,

CTSB

38, 23

40, 28

25, 16

D0-D4

D5-D7

44 - 48

1 - 3

2 - 6

7 - 9

27 - 31

32, 1, 2

Data bus (bidirectional). These pins are the eight bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least

significant bit and the first data bit in a transmit or receive serial data

stream.

I/O

Data set ready (active low). These inputs are associated with individual

UART channels A and B. A logic low on these pins indicates the modem or

data set is powered on and is ready for data exchange with the UART. The

state of these inputs is reflected in the modem status register (MSR).

DSRA,

DSRB

39, 20

41, 25

–

Data terminal ready (active low). These outputs are associated with

individual UART channels A and B. A logic low on these pins indicates that

theTLl16C2550 is powered on and ready. These pins can be controlled

through the modem control register. Writing a 1 to MCR bit 0 sets the DTR

output to low, enabling the modem. The output of these pins is high after

writing a 0 to MCR bit 0, or after a reset.

DTRA,

DTRB

34, 35

37, 38

–

GND

Signal and power ground.

Interrupt A and B (active high). These pins provide individual channel

interrupts, INT A and B. INT A and B are enabled when MCR bit 3 is set to

a logic 1, interrupt sources are enabled in the interrupt enable register

(IER). Interrupt conditions include: receiver errors, available receiver buffer

data, available transmit buffer space or when a modem status flag is

detected. INTA-B are in the high-impedance state after reset.

INTA,

INTB

30, 29

33, 32

22, 21

Read input (active low strobe). A high to low transition on IOR will load the

contents of an internal register defined by address bits A0-A2 onto the

TL16C2550 data bus (D0-D7) for access by an external CPU.

IOR

Write input (active low strobe). A low to high transition on IOW will transfer

the contents of the data bus (D0-D7) from the external CPU to an internal

IOW

–

12, 24, 25,

9, 17

No internal connection

User defined outputs. This function is associated with individual channels A

and B. The state of these pins is defined by the user through the software

settings of the MCR register, bit 3. INTA-B are set to active mode and OP

to a logic 0 when the MCR-3 is set to a logic 1. INTA-B are set to the

3-state mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3,

modem control register (MCR bit 3). The output of these two pins is high

after reset.

OPA, OPB

RESET

32, 9

35, 15

–

Reset. RESET will reset the internal registers and all the outputs. The

UART transmitter output and the receiver input will be disabled during reset

time. See TL16C2550 external reset conditions for initialization details.

RESET is an active-high input.

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