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TL16C2550PFBG4 PDF预览

TL16C2550PFBG4

更新时间： 2024-02-10 20:38:31
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
页数 文件大小 规格书
47页 1091K
描述
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS

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TL16C2550PFBG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：TQFP-48针数：48
Reach Compliance Code：compliantHTS代码：8542.31.00.01
Factory Lead Time：6 weeks风险等级：5.74
Is Samacsys：N其他特性：ALSO OPERATES AT 1.8V MINIMUM SUPPLY AT 10MHZ
地址总线宽度：3边界扫描：NO
最大时钟频率：24 MHz通信协议：ASYNC, BIT
最大数据传输速率：0.1875 MBps外部数据总线宽度：8
JESD-30 代码：S-PQFP-G48JESD-609代码：e4
长度：7 mm低功率模式：NO
湿度敏感等级：2串行 I/O 数：2
端子数量：48最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP48,.35SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：1.8/5 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Serial IO/Communication Controllers最大压摆率：7.5 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches：1

TL16C2550PFBG4 数据手册

 浏览型号TL16C2550PFBG4的Datasheet PDF文件第3页浏览型号TL16C2550PFBG4的Datasheet PDF文件第4页浏览型号TL16C2550PFBG4的Datasheet PDF文件第5页浏览型号TL16C2550PFBG4的Datasheet PDF文件第7页浏览型号TL16C2550PFBG4的Datasheet PDF文件第8页浏览型号TL16C2550PFBG4的Datasheet PDF文件第9页 
TL16C2550  
www.ti.com  
SLWS161D–JUNE 2005–REVISED OCTOBER 2006  
ACE1  
ACE2  
Parallel  
RX  
TX  
Serial to  
Parallel  
to Serial  
RCV  
FIFO  
XMT  
FIFO  
RTS  
CTS  
Flow  
Flow  
Control  
Control  
D7−D0  
D7−D0  
TX  
RX  
Parallel  
to Serial  
Serial to  
Parallel  
XMT  
FIFO  
RCV  
FIFO  
CTS  
RTS  
Flow  
Flow  
Control  
Control  
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example  
Auto-CTS (See Figure 2)  
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next  
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last  
stop bit that is currently being sent (see Figure 1). The auto-CTS function reduces interrupts to the host system.  
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically  
controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and  
a receiver overrun error may result.  
Auto-RTS (See Figure 3 and Figure 4)  
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and  
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of  
1, 4, or 8 (see Figure 2), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an  
additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because  
it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is  
automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.  
When the trigger level is 14 (see Figure 3), RTS is deasserted after the first data bit of the 16th character is  
present on the RX line. RTS is reasserted when the RCV FIFO has at least one available byte space.  
Enabling Autoflow Control and Auto-CTS  
Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a  
1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem  
control register should be cleared (this assumes that a control signal is driving CTS).  
Auto-CTS and Auto-RTS Functional Timing  
Start Bits 0−7  
Start Bits 0−7  
Start Bits 0−7  
Stop  
Stop  
Stop  
SOUT  
CTS  
Figure 2. CTS Functional Timing Waveforms  
6
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