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TL16C2550PFBG4 PDF预览

TL16C2550PFBG4

更新时间： 2024-02-25 02:50:45
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
页数 文件大小 规格书
47页 1091K
描述
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS

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TL16C2550PFBG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：TQFP-48针数：48
Reach Compliance Code：compliantHTS代码：8542.31.00.01
Factory Lead Time：6 weeks风险等级：5.74
Is Samacsys：N其他特性：ALSO OPERATES AT 1.8V MINIMUM SUPPLY AT 10MHZ
地址总线宽度：3边界扫描：NO
最大时钟频率：24 MHz通信协议：ASYNC, BIT
最大数据传输速率：0.1875 MBps外部数据总线宽度：8
JESD-30 代码：S-PQFP-G48JESD-609代码：e4
长度：7 mm低功率模式：NO
湿度敏感等级：2串行 I/O 数：2
端子数量：48最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP48,.35SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：1.8/5 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Serial IO/Communication Controllers最大压摆率：7.5 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches：1

TL16C2550PFBG4 数据手册

 浏览型号TL16C2550PFBG4的Datasheet PDF文件第1页浏览型号TL16C2550PFBG4的Datasheet PDF文件第3页浏览型号TL16C2550PFBG4的Datasheet PDF文件第4页浏览型号TL16C2550PFBG4的Datasheet PDF文件第5页浏览型号TL16C2550PFBG4的Datasheet PDF文件第6页浏览型号TL16C2550PFBG4的Datasheet PDF文件第7页 
TL16C2550  
www.ti.com  
SLWS161D–JUNE 2005–REVISED OCTOBER 2006  
PFB PACKAGE  
(TOP VIEW)  
Each ACE is a speed and voltage range upgrade of  
the TL16C550C, which in turn is a functional  
upgrade of the TL16C450. Functionally equivalent to  
the TL16C450 on power up or reset (single character  
or TL16C450 mode), each ACE can be placed in an  
alternate FIFO mode. This relieves the CPU of  
excessive software overhead by buffering received  
and to be transmitted characters. Each receiver and  
transmitter store up to 16 bytes in their respective  
FIFOs, with the receive FIFO including three  
additional bits per byte for error status. In the FIFO  
mode, a selectable autoflow control feature can  
significantly reduce software overload and increase  
system efficiency by automatically controlling serial  
data flow using handshakes between the RTS#  
output and CTS# input, thus eliminating overruns in  
the receive FIFO.  
48 47 46 45 44 43 42 41 40 39 38 37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
RESET  
DTRB  
DTRA  
RTSA  
OPA  
RXRDYA  
INTA  
INTB  
A0  
D5  
D6  
1
2
D7  
3
RXB  
RXA  
TXRDYB  
TXA  
4
5
6
TL16C2550PFB  
7
8
TXB  
9
OPB  
CSA  
CSB  
NC  
10  
11  
12  
A1  
A2  
NC  
Each ACE performs serial-to-parallel conversions on  
data received from a peripheral device or modem  
and stores the parallel data in its receive buffer or  
FIFO, and each ACE performs parallel-to-serial  
conversions on data sent from its CPU after storing  
the parallel data in its transmit buffer or FIFO. The  
CPU can read the status of either ACE at any time.  
Each ACE includes complete modem control  
capability and a processor interrupt system that can  
be tailored to the application.  
13 14 15 16 17 18 19 20 21 22 23 24  
NC−No internal connection  
FN PACKAGE  
(TOP VIEW)  
Each ACE includes a programmable baud rate  
generator capable of dividing a reference clock with  
divisors from 1 to 65535, thus producing a 16×  
internal reference clock for the transmitter and  
receiver logic. Each ACE accommodates up to a  
1.5-Mbaud serial data rate (24-MHz input clock). As  
a reference point, that speed would generate a  
667-ns bit time and a 6.7-µs character time (for 8,N,1  
serial data), with the internal clock running at 24  
MHz.  
6
5
4
3
2
1 44 43 42 41 40  
D5  
D6  
D7  
39  
38  
37  
RESET  
DTRB  
DTRA  
7
8
9
RXB  
RXA  
10  
11  
12  
13  
36  
35  
RTSA  
OPA  
TL16C2550FN  
TXRDYB  
TXA  
34  
33  
32  
31  
RXRDYA  
INTA  
TXB  
INTB  
A0  
14  
15  
Each ACE has a TXRDY# and RXRDY# output that  
can be used to interface to a DMA controller.  
OPB  
CSA  
CSB  
30  
29  
A1  
A2  
16  
17  
18 19 20 21 22 23 24 25 26 27 28  
2
Submit Documentation Feedback  
1234567...47

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